Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0) – Offset 104
Note: if a GPIO is not available, the corresponding register bit is reserved.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:24 | 0h | RO | Reserved (RSVD_0) Reserved |
| 23 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_23) Same description as bit 0. |
| 22 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_22) Same description as bit 0. |
| 21 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_21) Same description as bit 0. |
| 20 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_20) Same description as bit 0. |
| 19 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_19) Same description as bit 0. |
| 18 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_18) Same description as bit 0. |
| 17 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_17) Same description as bit 0. |
| 16 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_16) Same description as bit 0. |
| 15 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_15) Same description as bit 0. |
| 14 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_14) Same description as bit 0. |
| 13 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_13) Same description as bit 0. |
| 12 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_12) Same description as bit 0. |
| 11 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_11) Same description as bit 0. |
| 10 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_10) Same description as bit 0. |
| 9 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_9) Same description as bit 0. |
| 8 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_8) Same description as bit 0. |
| 7 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_7) Same description as bit 0. |
| 6 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_6) Same description as bit 0. |
| 5 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_5) Same description as bit 0. |
| 4 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_4) Same description as bit 0. |
| 3 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_3) Same description as bit 0. |
| 2 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_2) Same description as bit 0. |
| 1 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_1) Same description as bit 0. |
| 0 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sd_0) PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read-Only and software writes to the register have no effect. |