Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
ID | Date | Version | Classification |
---|---|---|---|
834819 | 01/29/2025 | 001 | Public |
Pad Ownership (PAD_OWN_GPP_B_2) – Offset b8
Note: if a GPIO is not available, the corresponding register bit is reserved.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:14 | 0h | RO | Reserved (RSVD_0) Reserved |
13:12 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_sb_19) Same description as bits[1:0]. |
11:10 | 0h | RO | Reserved (RSVD_1) Reserved |
9:8 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_sb_18) Same description as bits[1:0]. |
7:6 | 0h | RO | Reserved (RSVD_2) Reserved |
5:4 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_sb_17) Same description as bits[1:0]. |
3:2 | 0h | RO | Reserved (RSVD_3) Reserved |
1:0 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_sb_16) 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. No read/write restriction to the Pad Configuration register set during host ownership During host ownership, CSME and ISH do not own this pad and are not notified of the GPIO input event. |