Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
ID | Date | Version | Classification |
---|---|---|---|
834819 | 01/29/2025 | 001 | Public |
Power Management 1 Control (PM1_CNT) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:14 | 0h | RO | Reserved (Rsvd)
|
13 | 0h | WO | Sleep Enable (SLP_EN) This is a write-only bit and reads to it always return a zero. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. |
12:10 | 0h | RW | Sleep Type (SLP_TYP) This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1. These bits are reset by RTCRST# only. |
9:3 | 0h | RO | Reserved (Rsvd_1)
|
2 | 0h | WO | GBL_RLS (GBL_RLS) This bit is used by the ACPI software to raise an event to the BIOS software. BIOS software has a corresponding enable and status bits to control its ability to receive ACPI events. This bit always reads as 0. |
1 | 0h | RW | BM_RLD (BM_RLD) This bit is treated as a scratchpad bit. |
0 | 0h | RW | SCI Enable (SCI_EN) Selects the SCI interrupt or the SMI# for various events. When this bit is 1, then the events will generate an SCI interrupt. When this bit is 0, these events will generate an SMI#. |