31:29

0h

RW

Power Button Override Period (PBOP)

This field determines, while the power button remains asserted, how long the PMC will wait before initiating a global reset.
Encoding:
000b - 4 seconds
001b - 6 seconds
010b - 8 seconds
011b - 10 seconds
100b - 12 seconds
101b - 14 seconds
Others - Reserved

28

0h

RW/L

Power Button Native Mode Disable (PB_​DIS)

When this bit is '0' (default), the PMC's power button logic will act upon the input value
from the GPIO unit, as normal.
When this bit is set to '1', the PMC must force its internal version of the power button
pin to '1'. This will result in the PMC logic constantly seeing the pin as de-asserted.
This bit is not writable when ETR3.PB_​DIS_​LOCK bit is set.

27

0h

RO

Reserved

26

0h

RW/V

DRAM_​RESET# Control (DRAM_​RESET_​CTL)

BIOS uses this bit to control the DRAM_​RESET# pin, which is routed to the reset pin on the DRAM.
Encoding:
0 - DRAM_​RESET# = '0'
1 - DRAM_​RESET# output is tri-stated.
Note: This bit is cleared to '0' by HW when SLP_​S4# goes low.

25:0

0h

RO

Reserved