31:23

0h

RO

Reserved

22

1h

RW/L

Sys Reset# Suppression (SYS_​RST_​SUP)

: Do not suppress SYS_​RESET# input during a Dirty Warm Reset. 1: Suppress (ignore) SYS_​RESET# input during a Dirty Warm Reset. SYS_​RESET# triggered Resets will be ignored if this bit is set. Note: This register bit must be locked by BIOS using PM_​CFG.DBG_​MODE_​LOCK

21:18

0h

RW

HOST Miscellaneous DSW PM Configuration (HOST_​MISC_​DSW_​CFG)

These bits are defined as follows:
[21:19] - [b]Reserved
[18] - SYS_​PWROK Deglitch Enable (SYS_​PWROK_​DG_​EN)
Enables an 80ns deglitch filter on the SYS_​PWROK pin.

17

0h

RW

Host Wireless LAN Phy Power Enable (HOST_​WLAN_​PP_​EN)

This policy bit is set by Host software when it desires the wireless LAN PHY to be powered in Sx power states for wakes over wireless LAN (WoWLAN).

16

0h

RW

Deep-Sx WLAN Phy Power Enable (DSX_​WLAN_​PP_​EN)

When set to 1, PMC will keep SLP_​WLAN# high in deep-Sx to enable WoWLAN.
Note:
(1) This policy bit will be applied for deep-Sx entry from S3, S4 and S5.
(2) This bit does not affect SLP_​WLAN# behaviour in Sx after G3 or after a global reset
(3) HOST_​WLAN_​PP_​EN must be set when this bit is set.

15:0

0h

RO

Reserved