15

0h

RW/1C/V

Detected Parity Error (DPE)

Set when the root port receives a command or data from the backbone with a parity error. This is set even if PCMD.PERE is not set.

14

0h

RW/1C/V

Signaled System Error (SSE)

Set when the root port signals a system error to the internal SERR logic.

13

0h

RW/1C/V

Received Master Abort (RMA)

Set when the root port receives a completion with unsupported request status from the backbone.

12

0h

RW/1C/V

Received Target Abort (RTA)

Set when the root port receives a completion with completer abort from the backbone.

11

0h

RW/1C/V

Signaled Target Abort (STA)

Set whenever the root port forwards a target abort received from the downstream device onto the backbone.

10:9

0h

RO

Primary DEVSEL Timing Status (PDTS)

Reserved per PCI-Express spec

8

0h

RW/1C/V

Master Data Parity Error Detected (DPD)

Set when the root port receives a completion with a data parity error on the backbone and PCMD.PERE is set.

7

0h

RO

Primary Fast Back to Back Capable (PFBC)

Reserved per PCI-Express spec.

6

0h

RO

Reserved

5

0h

RO

Primary 66 MHz Capable (PC66)

Reserved per PCI-Express spec.

4

1h

RO

Capabilities List (CLIST)

Indicates the presence of a capabilities list.

3

0h

RO/V

Interrupt Status (IS)

Indicates status of hot plug and power management interrupts on the root port that result in INTx message generation. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of CMD.ID.

2:0

0h

RO

Reserved