7:4

0h

RSV

Reserved (RSVD)

Reserved

3

0h

RW

Full Reset (FULL_​RST)

When this bit is set to 1 and bit 1 is set to 1 (indicating Hard Reset, not Soft Reset), and the RST_​CPU bit (bit 2) is written from 0 to 1, a full reset will occur with SLP_​S3#, SLP_​S4# and SLP_​S5# active (low) for at least 3 (and no more than 5) seconds.
When this bit is set, it also causes the full power cycle (SLP_​S3/4/5# assertion) in response to SYSRESET#, PWROK#, and Watchdog timer reset sources.

2

0h

RW

Reset CPU (RST_​CPU)

This bit will cause either a hard or soft reset to the CPU depending on the state of the SYS_​RST bit (bit 1 in this same register). The software will cause the reset by setting bit 2 from a 0 to a 1.

1

0h

RW

System Reset (SYS_​RST)

This bit determines the type of reset caused via RST_​CPU (bit 2 of this register). If SYS_​RST is 0 when RST_​CPU goes from 0 to 1, then the SOC will force INIT# active for 16 PCI clocks. If SYS_​RST is 1 when RST_​CPU goes from 0 to 1, then the SOC will force PCI reset active for about 1 ms, however the SLP_​S3#, SLP_​S4# and SLP_​S5# signals assertion is dependent on the value of the FULL_​RST (bit3 of this register).

0

0h

RSV

Reserved (RSVD_​1)

Reserved