Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
Introduction
8254 Timer I/O
Advanced Programmable Interrupt (APIC) Index
Advanced Programmable Interrupt (APIC) Mem
Direct eSPI PCI Configuration
Direct eSPI PCR
GPIO Community 0
GPIO Community 1
High Precision Event Timer (HPET) MMIO
Interrupt I/O
Interrupt PCR
PCIe Configuration
PMC I/O
PMC MMIO
PMC PCI Configuration
Processor IO
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO
SPI MMIO
SPI PCI Configuration
SSRAM PCI Configuration
8254 Timer I/O
Counter 0_Interval Timer Status Byte Format Register (C0_ITSBFR)
Counter 0_Counter Access Ports Register (C0_CAPR)
Counter 2_Interval Timer Status Byte Format Register (C2_ITSBFR)
Counter 2_Counter Access Ports Register (C2_CAPR)
Timer Control Word Register (TCW)
Read Back Command (RBC)
Counter Latch Command (CLC)
Advanced Programmable Interrupt (APIC) Index
Identification Register (IDR)
Version Register (VS)
Redirection Table Entry 0 (RTE0)
Redirection Table Entry 1 (RTE1)
Redirection Table Entry 2 (RTE2)
Redirection Table Entry 3 (RTE3)
Redirection Table Entry 4 (RTE4)
Redirection Table Entry 5 (RTE5)
Redirection Table Entry 6 (RTE6)
Redirection Table Entry 7 (RTE7)
Redirection Table Entry 8 (RTE8)
Redirection Table Entry 9 (RTE9)
Redirection Table Entry 10 (RTE10)
Redirection Table Entry 11 (RTE11)
Redirection Table Entry 12 (RTE12)
Redirection Table Entry 13 (RTE13)
Redirection Table Entry 14 (RTE14)
Redirection Table Entry 15 (RTE15)
Redirection Table Entry 16 (RTE16)
Redirection Table Entry 17 (RTE17)
Redirection Table Entry 18 (RTE18)
Redirection Table Entry 19 (RTE19)
Redirection Table Entry 20 (RTE20)
Redirection Table Entry 21 (RTE21)
Redirection Table Entry 22 (RTE22)
Redirection Table Entry 23 (RTE23)
Redirection Table Entry 24 (RTE24)
Redirection Table Entry 25 (RTE25)
Redirection Table Entry 26 (RTE26)
Redirection Table Entry 27 (RTE27)
Redirection Table Entry 28 (RTE28)
Redirection Table Entry 29 (RTE29)
Redirection Table Entry 30 (RTE30)
Redirection Table Entry 31 (RTE31)
Redirection Table Entry 32 (RTE32)
Redirection Table Entry 33 (RTE33)
Redirection Table Entry 34 (RTE34)
Redirection Table Entry 35 (RTE35)
Redirection Table Entry 36 (RTE36)
Redirection Table Entry 37 (RTE37)
Redirection Table Entry 38 (RTE38)
Redirection Table Entry 39 (RTE39)
Redirection Table Entry 40 (RTE40)
Redirection Table Entry 41 (RTE41)
Redirection Table Entry 42 (RTE42)
Redirection Table Entry 43 (RTE43)
Redirection Table Entry 44 (RTE44)
Redirection Table Entry 45 (RTE45)
Redirection Table Entry 46 (RTE46)
Redirection Table Entry 47 (RTE47)
Redirection Table Entry 48 (RTE48)
Redirection Table Entry 49 (RTE49)
Redirection Table Entry 50 (RTE50)
Redirection Table Entry 51 (RTE51)
Redirection Table Entry 52 (RTE52)
Redirection Table Entry 53 (RTE53)
Redirection Table Entry 54 (RTE54)
Redirection Table Entry 55 (RTE55)
Redirection Table Entry 56 (RTE56)
Redirection Table Entry 57 (RTE57)
Redirection Table Entry 58 (RTE58)
Redirection Table Entry 59 (RTE59)
Redirection Table Entry 60 (RTE60)
Redirection Table Entry 61 (RTE61)
Redirection Table Entry 62 (RTE62)
Redirection Table Entry 63 (RTE63)
Redirection Table Entry 64 (RTE64)
Redirection Table Entry 65 (RTE65)
Redirection Table Entry 66 (RTE66)
Redirection Table Entry 67 (RTE67)
Redirection Table Entry 68 (RTE68)
Redirection Table Entry 69 (RTE69)
Redirection Table Entry 70 (RTE70)
Redirection Table Entry 71 (RTE71)
Redirection Table Entry 72 (RTE72)
Redirection Table Entry 73 (RTE73)
Redirection Table Entry 74 (RTE74)
Redirection Table Entry 75 (RTE75)
Redirection Table Entry 76 (RTE76)
Redirection Table Entry 77 (RTE77)
Redirection Table Entry 78 (RTE78)
Redirection Table Entry 79 (RTE79)
Redirection Table Entry 80 (RTE80)
Redirection Table Entry 81 (RTE81)
Redirection Table Entry 82 (RTE82)
Redirection Table Entry 83 (RTE83)
Redirection Table Entry 84 (RTE84)
Redirection Table Entry 85 (RTE85)
Redirection Table Entry 86 (RTE86)
Redirection Table Entry 87 (RTE87)
Redirection Table Entry 88 (RTE88)
Redirection Table Entry 89 (RTE89)
Redirection Table Entry 90 (RTE90)
Redirection Table Entry 91 (RTE91)
Redirection Table Entry 92 (RTE92)
Redirection Table Entry 93 (RTE93)
Redirection Table Entry 94 (RTE94)
Redirection Table Entry 95 (RTE95)
Redirection Table Entry 96 (RTE96)
Redirection Table Entry 97 (RTE97)
Redirection Table Entry 98 (RTE98)
Redirection Table Entry 99 (RTE99)
Redirection Table Entry 100 (RTE100)
Redirection Table Entry 101 (RTE101)
Redirection Table Entry 102 (RTE102)
Redirection Table Entry 103 (RTE103)
Redirection Table Entry 104 (RTE104)
Redirection Table Entry 105 (RTE105)
Redirection Table Entry 106 (RTE106)
Redirection Table Entry 107 (RTE107)
Redirection Table Entry 108 (RTE108)
Redirection Table Entry 109 (RTE109)
Redirection Table Entry 110 (RTE110)
Redirection Table Entry 111 (RTE111)
Redirection Table Entry 112 (RTE112)
Redirection Table Entry 113 (RTE113)
Redirection Table Entry 114 (RTE114)
Redirection Table Entry 115 (RTE115)
Redirection Table Entry 116 (RTE116)
Redirection Table Entry 117 (RTE117)
Redirection Table Entry 118 (RTE118)
Redirection Table Entry 119 (RTE119)
Direct eSPI PCI Configuration
Device and Vendor Identifiers (ESPI_DID_VID)
Device Status and Command (ESPI_STS_CMD)
Class Code and Revision ID (ESPI_CC_RID)
Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT)
Sub System Identifiers (ESPI_SS)
Capability List Pointer (ESPI_CAPP)
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)
eSPI Generic IO Range 1 (ESPI_LGIR1)
eSPI Generic IO Range 2 (ESPI_LGIR2)
eSPI Generic IO Range 3 (ESPI_LGIR3)
eSPI Generic IO Range 4 (ESPI_LGIR4)
USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)
eSPI Generic Memory Range (ESPI_LGMR)
BIOS Decode Enable (ESPI_BDE)
BIOS Control (ESPI_BC)
Direct eSPI PCR
eSPI Device Configuration Register And Link Control (SLV_CFG_REG_CTL)
eSPI Device Configuration Register Data (SLV_CFG_REG_DATA)
Peripheral Channel Error for Device 0 (PCERR_SLV0)
Virtual Wire Channel Error for Device 0 (VWERR_SLV0)
Flash Access Channel Error for Device 0 (FCERR_SLV0)
Link Error for Device 0 (LNKERR_SLV0)
GPIO Community 0
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_A_1)
Pad Ownership (PAD_OWN_GPP_A_2)
Pad Configuration Lock (PADCFGLOCK_GPP_A_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0)
GPI Interrupt Status (GPI_IS_GPP_A_0)
GPI Interrupt Enable (GPI_IE_GPP_A_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sa_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sa_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sa_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sa_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sa_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sa_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sa_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sa_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sa_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sa_23)
GPIO Community 1
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_B_0)
Pad Ownership (PAD_OWN_GPP_B_1)
Pad Ownership (PAD_OWN_GPP_B_2)
Pad Ownership (PAD_OWN_GPP_D_0)
Pad Ownership (PAD_OWN_GPP_D_1)
Pad Ownership (PAD_OWN_GPP_D_2)
Pad Configuration Lock (PADCFGLOCK_GPP_B_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0)
Pad Configuration Lock (PADCFGLOCK_GPP_D_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)
GPI Interrupt Status (GPI_IS_GPP_B_0)
GPI Interrupt Status (GPI_IS_GPP_D_0)
GPI Interrupt Enable (GPI_IE_GPP_B_0)
GPI Interrupt Enable (GPI_IE_GPP_D_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)
SMI Status (GPI_SMI_STS_GPP_B_0)
SMI Status (GPI_SMI_STS_GPP_D_0)
SMI Enable (GPI_SMI_EN_GPP_B_0)
SMI Enable (GPI_SMI_EN_GPP_D_0)
NMI Status (GPI_NMI_STS_GPP_B_0)
NMI Status (GPI_NMI_STS_GPP_D_0)
NMI Enable (GPI_NMI_EN_GPP_B_0)
NMI Enable (GPI_NMI_EN_GPP_D_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_B)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sb_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sb_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_sd_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_sd_23)
High Precision Event Timer (HPET) MMIO
General Capabilities and ID Register (GEN_CAP_ID)
General Config Register (GEN_CFG)
General Interrupt Status Register (GEN_INT_STS)
Main Counter Value (MAIN_CNTR)
Timer 0 Config and Capabilities (TMR0_CNF_CAP)
Timer 0 Comparator Value (TMR0_CMP_VAL)
Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)
Timer 1 Config and Capabilities (TMR1_CNF_CAP)
Timer 1 Comparator Value (TMR1_CMP_VAL)
Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)
Timer 2 Config and Capabilities (TMR2_CNF_CAP)
Timer 2 Comparator Value (TMR2_CMP_VAL)
Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)
Timer 3 Config and Capabilities (TMR3_CNF_CAP)
Timer 3 Comparator Value (TMR3_CMP_VAL)
Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)
Timer 4 Config and Capabilities (TMR4_CNF_CAP)
Timer 4 Comparator Value (TMR4_CMP_VAL)
Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)
Timer 5 Config and Capabilities (TMR5_CNF_CAP)
Timer 5 Comparator Value (TMR5_CMP_VAL)
Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)
Timer 6 Config and Capabilities (TMR6_CNF_CAP)
Timer 6 Comparator Value (TMR6_CMP_VAL)
Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)
Timer 7 Config and Capabilities (TMR7_CNF_CAP)
Timer 7 Comparator Value (TMR7_CMP_VAL)
Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)
Interrupt I/O
Master Initialization Command Word 1 (MICW1)
Master Operational Control Word 2 (MOCW2)
Master Operational Control Word 3 (MOCW3)
Master Initialization Command Word 2 (MICW2)
Master Initialization Command Word 3 (MICW3)
Master Initialization Command Word 4 (MICW4)
Master Operational Control Word 1 (MOCW1)
Slave Operational Control Word 3 (SOCW3)
Slave Initialization Command Word 1 (SICW1)
Slave Operational Control Word 2 (SOCW2)
Slave Initialization Command Word 2 (SICW2)
Slave Initialization Command Word 3 (SICW3)
Slave Initialization Command Word 4 (SICW4)
Slave Operational Control Word 1 (SOCW1)
Master Edge/Level Control (ELCR1)
Slave Edge/Level Control (ELCR2)
Interrupt PCR
PIRQA Routing Control (PARC)
PIRQB Routing Control (PBRC)
PIRQC Routing Control (PCRC)
PIRQD Routing Control (PDRC)
PIRQE Routing Control (PERC)
PIRQF Routing Control (PFRC)
PIRQG Routing Control (PGRC)
PIRQH Routing Control (PHRC)
Message Decoder Control (MSGDC)
PCI Interrupt Route 0 (PIR0)
PCI Interrupt Route 1 (PIR1)
PCI Interrupt Route 2 (PIR2)
PCI Interrupt Route 3 (PIR3)
PCI Interrupt Route 4 (PIR4)
PCI Interrupt Route 5 (PIR5)
PCI Interrupt Route 6 (PIR6)
PCI Interrupt Route 7 (PIR7)
PCI Interrupt Route 8 (PIR8)
PCI Interrupt Route 9 (PIR9)
PCI Interrupt Route 10 (PIR10)
PCI Interrupt Route 11 (PIR11)
PCI Interrupt Route 12 (PIR12)
PCI Interrupt Route 13 (PIR13)
PCI Interrupt Route 14 (PIR14)
PCI Interrupt Route 15 (PIR15)
PCI Interrupt Route 16 (PIR16)
PCI Interrupt Route 17 (PIR17)
PCI Interrupt Route 18 (PIR18)
PCI Interrupt Route 19 (PIR19)
PCI Interrupt Route 20 (PIR20)
PCI Interrupt Route 21 (PIR21)
PCI Interrupt Route 22 (PIR22)
PCI Interrupt Route 23 (PIR23)
PCI Interrupt Route 24 (PIR24)
PCI Interrupt Route 25 (PIR25)
PCI Interrupt Route 26 (PIR26)
PCI Interrupt Route 27 (PIR27)
PCI Interrupt Route 28 (PIR28)
PCI Interrupt Route 29 (PIR29)
PCI Interrupt Route 30 (PIR30)
PCI Interrupt Route 31 (PIR31)
General Interrupt Control (GIC)
Interrupt Polarity Control 0 (IPC0)
Interrupt Polarity Control 1 (IPC1)
Interrupt Polarity Control 2 (IPC2)
Interrupt Polarity Control 3 (IPC3)
Interrupt Blocking Control (IBC)
Interrupt Edge-Trigger Extension 0 (IETE0)
Interrupt Edge-Trigger Extension 1 (IETE1)
Interrupt Edge-Trigger Extension 2 (IETE2)
Interrupt Edge-Trigger Extension 3 (IETE3)
ITSS Power Reduction Control (ITSSPRC)
SIDE Clock Timing (SIDECT)
IPCI Clock Timing (IPCICT)
PGCB Clock Timing (PGCBCT)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Mask (CEM)
NMI Control (NMI)
Master Message Control (MMC)
Master Message Status (MMSTS)
HPET Offload Scale Value (HOFFVAL)
PCIe Configuration
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Header Log (HL_DW1)
Header Log (HL_DW2)
Header Log (HL_DW3)
Header Log (HL_DW4)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
TLP Prefix Log 1 (TLPPL1)
TLP Prefix Log 2 (TLPPL2)
TLP Prefix Log 3 (TLPPL3)
TLP Prefix Log 4 (TLPPL4)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
PMC I/O
Power Management 1 Enables and Status (PM1_EN_STS)
Power Management 1 Control (PM1_CNT)
Power Management 1 Timer (PM1_TMR)
General Purpose Event 1 Status [31:0] (GPE1_STS_31_0)
General Purpose Event 1 Status [63:32] (GPE1_STS_63_32)
General Purpose Event 1 Status [63:32] (GPE1_STS_95_64)
General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0)
General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32)
General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64)
SMI Control and Enable (SMI_EN)
SMI Status Register (SMI_STS)
General Purpose Event Control (GPE_CTRL)
Device Activity Status Register (DEVTRAP_STS)
Therm Timer Delay Register (THERM_TIMER_DELAY)
PM2a Control Block (PM2A_CNT_BLK)
Over-Clocking WDT Control (OC_WDT_CTL)
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)
General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)
General Purpose Event 0 Status [127:96] (GPE0_STS_127_96)
General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)
General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)
General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)
General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
PMC MMIO
General PM Configuration A (GEN_PMCON_A)
General PM Configuration B (GEN_PMCON_B)
Configured Revision ID (CRID)
Extended Test Mode Register 3 (ETR3)
SET STRAP MSG LOCK (SSML)
SET STRAP MSG CONTROL (SSMC)
SET STRAP MSG DATA (SSMD)
Configured Revision ID (CRID_UIP)
SLP S0 DEBUG REG0 (SLP_S0_DBG_0)
SLP S0 DEBUG REG1 (SLP_S0_DBG_1)
SLP S0 DEBUG REG2 (SLP_S0_DBG_2)
HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1)
HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2)
HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3)
HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)
HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)
HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6)
EXT FET RAMP CFG (EXT_FET_RAMP_CFG)
VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)
Always Running Timer Value 31:0 (ARTV_31_0)
Always Running Timer Value 31:0 (ARTV_63_32)
Always Running Timer Value Control (ARTV_CTRL)
Timed GPIO Control 0 (TGPIOCTL0)
Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32)
Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0)
Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0)
Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32)
Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)
Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)
Timed GPIO Control 1 (TGPIOCTL1)
Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32)
Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0)
Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0)
Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32)
Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)
Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)
Min Temperature (MIN_TEMP)
Max Temperature (MAX_TEMP)
EC Thermal Sensor Reporting Enable (ECRPTEN)
Throttle Level (TL)
SW Throttle (SWTHROT)
Throttle Levels Enable (TLEN)
Thermal Sensor Alert High Value (TSAHV)
Thermal Sensor Alert Low Value (TSALV)
Thermal Alert Trip Status (TAS)
PCH Hot Level Control (PHLC)
Temperature Sensor Control and Status (TSS0)
SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL)
Wake Alarm Device Timer: AC (WADT_AC)
Wake Alarm Device Timer: DC (WADT_DC)
Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)
Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)
Power and Reset Status (PRSTS)
Power Management Configuration Reg 1 (PM_CFG)
S3 Power Gating Policies (S3_PWRGATE_POL)
S4 Power Gating Policies (S4_PWRGATE_POL)
S5 Power Gating Policies (S5_PWRGATE_POL)
DeepSx Configuration (DSX_CFG)
Power Management Configuration Reg 2 (PM_CFG2)
Power Management Configuration Reg 3 (PM_CFG3)
CPU Early Power-on Configuration (CPU_EPOC)
ACPI Timer Control (ACPI_TMR_CTL)
Last TSC Alarm Value[31:0] (TSC_ALARM_LO)
Last TSC Alarm Value[63:32] (TSC_ALARM_HI)
GPIO Configuration (GPIO_CFG)
Global Reset Causes 0 (GBLRST_CAUSE0)
Global Reset Causes 1 (GBLRST_CAUSE1)
Host Partition Reset Causes (HPR_CAUSE0)
Latency Limit Residency 0 (LAT_LIM_RES_0)
Latency Limit Residency 1 (LAT_LIM_RES_1)
Latency Limit Residency 2 (LAT_LIM_RES_2)
SLP_S0 Residency (SLP_S0_RESIDENCY)
Latency Limit Control (LATENCY_LIMIT_CONTROL)
ACPI Control (ACTL)
S0 Residency (S0_RES)
PGD PG_ACK Status Register 0 (PPASR0)
PGD PG_ACK Status Register 1 (PPASR1)
PGD PFET Enable Ack Status Register 0 (PPFEAR0)
PGD PFET Enable Ack Status Register 1 (PPFEAR1)
PGD PG_REQ Status Register 0 (PPRSR0)
PGD PG_REQ Status Register 1 (PPRSR1)
ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1)
ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)
PMC PCI Configuration
Device Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
Cache Line Latency Header And BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register 1 (BAR1)
Base Address Register 1 High (BAR1_HIGH)
Base Address Register2 (BAR2)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
PowerManagement Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device Vendor Specific (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
SMBus MMIO and I/O
Host Status Register Address (HSTS)
Host Control Register (HCTL)
Host Command Register (HCMD)
Transmit Target Address Register (TSA)
Data 0 Register (HD0)
Data 1 Register (HD1)
Host Block Data (HBD)
Packet Error Check Data Register (PEC)
Receive Target Address Register (RSA)
Target Data Register (SD)
Auxiliary Status (AUXS)
Auxiliary Control (AUXC)
SMLINK_PIN_CTL Register (SMLC)
SMBUS_PIN_CTL Register (SMBC)
Target Status Register (SSTS)
Target Command Register (SCMD)
Notify Device Address Register (NDA)
Notify Data Low Byte Register (NDLB)
Notify Data High Byte Register (NDHB)
SMBus PCI Configuration
Vendor ID (VID)
Device ID (DID)
Command Register (CMD)
Device Status (DS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
SMBus Memory Base Address_31_0 (SMBMBAR_31_0)
SMBus Memory Base Address_63_32 (SMBMBAR_63_32)
SMB Base Address (SBA)
Subsystem Vendor Identifiers (SVID)
Subsystem Identifiers (SID)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Host Configuration (HCFG)
TCO Base Address (TCOBASE)
TCO Control (TCOCTL)
SMBus Configuration Register 80 (SMBSM)
SPI MMIO
BIOS Flash Primary Region (BIOS_BFPREG)
Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL)
Flash Address (BIOS_FADDR)
Discrete Lock Bits (BIOS_DLOCK)
Flash Data (BIOS_FDATA0)
Flash Data (BIOS_FDATA1)
Flash Data (BIOS_FDATA2)
Flash Data (BIOS_FDATA3)
Flash Data (BIOS_FDATA4)
Flash Data (BIOS_FDATA5)
Flash Data (BIOS_FDATA6)
Flash Data (BIOS_FDATA7)
Flash Data (BIOS_FDATA8)
Flash Data (BIOS_FDATA9)
Flash Data (BIOS_FDATA10)
Flash Data (BIOS_FDATA11)
Flash Data (BIOS_FDATA12)
Flash Data (BIOS_FDATA13)
Flash Data (BIOS_FDATA14)
Flash Data (BIOS_FDATA15)
Flash Region Access Permissions (BIOS_FRACC)
Flash Region (BIOS_FREG0)
Flash Region (BIOS_FREG1)
Flash Region (BIOS_FREG2)
Flash Region (BIOS_FREG3)
Flash Region (BIOS_FREG4)
Flash Region (BIOS_FREG5)
Flash Region (BIOS_FREG6)
Flash Region (BIOS_FREG7)
Flash Region (BIOS_FREG8)
Flash Region (BIOS_FREG9)
Flash Region (BIOS_FREG10)
Flash Region (BIOS_FREG11)
Flash Protected Range (BIOS_FPR0)
Flash Protected Range (BIOS_FPR1)
Flash Protected Range (BIOS_FPR2)
Flash Protected Range (BIOS_FPR3)
Flash Protected Range (BIOS_FPR4)
Global Protected Range 0 (BIOS_GPR0)
Secondary Flash Region Access Permissions (BIOS_SFRACC)
Flash Descriptor Observability Control (BIOS_FDOC)
Flash Descriptor Observability Data (BIOS_FDOD)
Additional Flash Control (BIOS_AFC)
Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0)
Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1)
Parameter Table Index (BIOS_PTINX)
Parameter Table Data (BIOS_PTDATA)
SPI Bus Requester Status (BIOS_SBRS)
Flash Region (BIOS_FREG12)
Flash Region (BIOS_FREG13)
Flash Region (BIOS_FREG14)
Flash Region (BIOS_FREG15)
RPMC SFDP Table (BIOS_RPMC0_D0)
RPMC SFDP Table (BIOS_RPMC1_D0)
RPMC SFDP Table (BIOS_RPMC0_D1)
RPMC SFDP Table (BIOS_RPMC1_D1)
BIOS Master Read Access Permissions (BIOS_BM_RAP)
BIOS Master Write Access Permissions (BIOS_BM_WAP)
SPI PCI Configuration
Device ID and Vendor ID (BIOS_SPI_DID_VID)
Status and Command (BIOS_SPI_STS_CMD)
Revision ID and Class Code (BIOS_SPI_CC_RID)
BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS)
SPI BAR0 MMIO (BIOS_SPI_BAR0)
Subsystem and Vendor ID (BIOS_SPI_SID_SVID)
BIOS Direct Read DMA Base Address High (BIOS_RD_DMA_BA_HI)
BIOS Direct Read DMA Base Address (BIOS_RD_DMA_BA)
BIOS Direct Read DMA Base Offset (BIOS_RD_DMA_BASE_OFFSET)
BIOS Direct Read DMA Status (BIOS_RD_DMA_STS)
SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL)
BIOS Decode Enable (BIOS_SPI_BDE)
BIOS Control (BIOS_SPI_BC)
SPI BAR1 MMIO (BIOS_SPI_BAR1)
SSRAM PCI Configuration
Device Vendor ID (DEVVENDID)
STATUSCOMMAND Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)
CAPABILITY PTR (CAPABILITYPTR)
INTERRUPT REG Interrupt Register (INTERRUPTREG)
POWER CAP ID PowerManagement Capability ID (POWERCAPID)
PME CTRL STATUS (PMECTRLSTATUS)
PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)
DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
GEN REG RW1 (GEN_REGRW1)
GEN REG RW2 (GEN_REGRW2)
GEN REG RW3 (GEN_REGRW3)
GEN REG RW4 (GEN_REGRW4)
GEN INPUT REG (GEN_INPUT_REG)
Slave Edge/Level Control (ELCR2) – Offset 4d1
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 7:6 | 0h | RW | Edge Level Control (ELC_15_14) In edge mode, (bit cleared), the interrupt is recognized by a low to high transition. In level mode (bit set), the interrupt is recognized by a high level. Bit 7 applies to IRQ15, and bit 6 to IRQ14. |
| 5 | 0h | RW | Edge Level Control (ELC_13) In edge mode, (bit cleared), the interrupt is recognized by a low to high transition. In level mode (bit set), the interrupt is recognized by a high level. This bit applies to |
| 4:1 | 0h | RW | Edge Level Control (ELC_12_9) In edge mode, (bit cleared), the interrupt is recognized by a low to high transition. In level mode (bit set), the interrupt is recognized by a high level. Bit 4 applies to IRQ12, bit 3 to IRQ11, bit 2 to IRQ10, and bit 1 to IRQ9. |
| 0 | 0h | RW | Edge Level Control (ELC_8) The Real Time Clock (IRQ8#) cannot be programmed for level mode. |