Slave Initialization Command Word 1 (SICW1) – Offset a0 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special Mask Mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization sequence.

Bit Range	Default	Access	Field Name and Description
7:5	0h	WO	ICW/OCW select (ICW_OCW_SLT1) These bits are MCS-85 specific, and not needed. Should be programmed to 000
4	1h	WO	ICW/OCW select (ICW_OCW_SLT2) This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence.
3	0h	WO	Edge/Level Bank Select (LTIM) Disabled. Replaced by the edge/level triggered control registers (ELCR).
2	0h	WO	ADI IGNORED (ADI) Ignored for the SOC. Should be programmed to 0.
1	0h	WO	Single or Cascade (SNGL) Must be programmed to a 0 to indicate two controllers operating in cascade mode.
0	1h	WO	ICW4 Write Required (IC4) This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.

Slave Operational Control Word 2 (SOCW2)

Slave Operational Control Word 3 (SOCW3) Slave Operational Control Word 2 (SOCW2)

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Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Slave Initialization Command Word 1 (SICW1) – Offset a0