Slave Initialization Command Word 2 (SICW2) – Offset a1 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed for bits[7:3] is used by the CPU to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller.

Bit Range	Default	Access	Field Name and Description
7:3	0h	WO	Interrupt Vector Base Address (IVBA) Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input.
2:0	0h	WO	Interrupt Request Level (IRL) When writing ICW2, these bits should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code: Code Master Interrupt Slave Interrupt 000 IRQ0 IRQ8 001 IRQ1 IRQ9 010 IRQ2 IRQ10 011 IRQ3 IRQ11 100 IRQ4 IRQ12 101 IRQ5 IRQ13 110 IRQ6 IRQ14 111 IRQ7 IRQ15

Bit Range

Default

Access

Field Name and Description

7:3

Interrupt Vector Base Address (IVBA)

Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input.

2:0

Interrupt Request Level (IRL)

When writing ICW2, these bits should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code:

Code Master Interrupt Slave Interrupt

000 IRQ0 IRQ8

001 IRQ1 IRQ9

010 IRQ2 IRQ10

011 IRQ3 IRQ11

100 IRQ4 IRQ12

101 IRQ5 IRQ13

110 IRQ6 IRQ14

111 IRQ7 IRQ15

Slave Initialization Command Word 3 (SICW3)

Slave Operational Control Word 2 (SOCW2) Slave Initialization Command Word 3 (SICW3)

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Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Slave Initialization Command Word 2 (SICW2) – Offset a1