31

0h

RW

Latch SLP_​S0#events (LATCH_​SLPS0_​EVENTS)

When this bit is written to 1, the current state of SLP_​S0# events is latched and captured in SLP_​S0_​DEBUG_​REGx registers. A write of 0 has no effect though it is necessary to clear this register before writing a 1 to latch events the next time.
Note that writes to this register will bring CPU out of C10 and wake PLLs so its usage is limited to looking at certain low power entry events that are not affected by writes to this register.

30:8

0h

RO

Reserved

7

0h

RO/V

UFS1_​D3_​STS (UFS1_​D3_​STS)

This bit when 1 indicates that UFS1 controller is in D3 state (taking static/function disables into account as well)

6

0h

RO/V

UFS0_​D3_​STS (UFS0_​D3_​STS)

This bit when 1 indicates that UFS0 controller is in D3 state (taking static/function disables into account as well)

5

0h

RO/V

SATA_​D3_​STS (SATA_​D3_​STS)

This bit when 1 indicates that SATA controller is in D3 state (taking static/function disables into account as well)

4:3

0h

RO

Reserved

2

0h

RO/V

XHCI_​D3_​STS (XHCI_​D3_​STS)

This bit when 1 indicates that XHCI controller is in D3 state (taking static/function disables into account as well)

1

0h

RO/V

OTG_​D3_​STS (OTG_​D3_​STS)

This bit when 1 indicates that OTG controller is in D3 state (taking static/function disables into account as well)

0

0h

RO/V

AUDIO_​D3_​STS (AUDIO_​D3_​STS)

This bit when 1 indicates that Audio DSP controller is in D3 state (taking static/function disables into account as well)