31:15

0h

RO

Reserved

14

0h

RO/V

PMC ARC PG Ready IDLE (PMC_​ARC_​IDLE_​STS)

This bit when 1 indicates that the PMCs ARC microcontroller is ready for power gating

13

0h

RO/V

Platform ASLT greater than threshold Status (ASLT_​GT_​THRES_​STS)

This bit when 1 indicates that the platform ASLT is greater than threashold

12

0h

RO/V

PM_​SYNC States Inactive (PMSYNC_​STATE_​IDLE_​STS)

This bit when 1 indicates that PMSYNC requests are not active.

11

0h

RO

Reserved

10

0h

RO/V

CNV VNN REQ Status (CNV_​VNN_​REQ_​STS)

This bit when 1 indicates that CNV VNN Req is active.

9

0h

RO/V

CNV VNN AON REQ Status (CNV_​VNNAON_​REQ_​STS)

This bit when 1 indicates that CNV VNNAON Req is active.

8

0h

RO/V

ISH VNN REQ Status (ISH_​VNN_​REQ_​STS)

This bit when 1 indicates that ISH Vnn Req is active.

7

0h

RO/V

ISH VNN AON REQ Status (ISH_​VNNAON_​REQ_​STS)

This bit when 1 indicates that ISH VnnAON Req is active.

6

0h

RO/V

PCIe Low Power Status (PCIE_​LP_​STS)

This bit when 1 indicates that all PCIe root port controllers are in their low power state.

5

0h

RO/V

Thermal Sensor Disabled Status (TS_​DIS_​STS)

This bit when 1 indicates that the thermal sensor is disabled

4

0h

RO/V

GBE No Link Status (GBE_​NO_​LINK_​STS)

This bit when 1 indicates that the GBE interface is disconected.

3

0h

RO

Reserved

2

0h

RO/V

USB2 SUS Power Gated Status (USB2_​SUS_​PG_​STS)

This bit when 1 indicates that USB2 PHY SUS power domain is off.

1

0h

RO/V

CSME Power Gated Status (CSME_​PG_​STS)

This bit when 1 indicates that all power gated domains in CSME are turned off.

0

0h

RO/V

MHPY CORE Power Gated Status (MPHY_​CORE_​PG_​STS)

This bit when 1 indicates that HSIO core and data lanes are off.