SMBUS_PIN_CTL Register (SMBC) – Offset f - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
7:3	0h	RO	Reserved (RSVD) Reserved
2	1h	RW	SMBCLK_CTL (SMBCLK_CTL) 0 = The SMBCLK pin is dreven low, independent of what the other SMB logic would otherwise indicate for the SMBCLK pin. 1 = The SMBCLK pin is Not overdriven low. The other SMBus logic controls the state of the pin.
1	0h	RO/V	SMBDATA_CUR_STS (SMBDATA_CUR_STS) This bit has a default value that is dependent on an external signal level. This returns the value on the SMBDATA pin. It will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin.
0	0h	RO/V	SMBCLK_CUR_STS (SMBCLK_CUR_STS) This bit has a default value that is dependent on an external signal level. This returns the value on the SMBCLK pin. It will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin.

SMLINK_PIN_CTL Register (SMLC) Target Status Register (SSTS)