31

0h

RW

XHCI SMI Enable (XHCI_​SMI_​EN)

Software sets this bit to enable XHCI SMI events.

30

0h

RW

ME SMI Enable (ME_​SMI_​EN)

Software sets this bit to enable ME SMI# events.

29

0h

RW

LPSS SMI Enable (LPSS_​SMI_​EN)

Software sets this bit to enable I3C, I2C, UART, GSPI SMI events

28

0h

RW/L

eSPI SMI Enable (ESPI_​SMI_​EN)

Software sets this bit to enable eSPI SMI events.
NOTE: When the ESPI_​SMI_​LOCK bit is set, this bit cannot be changed.

27

0h

RW/1S

GPIO Unlock SMI Enable (GPIO_​UNLOCK_​SMI_​EN)

Setting this bit will cause an SMI# to be generated when the GPIO_​UNLOCK_​SMI_​STS bit is set in the SMI_​STS register.

Once written to '1' , this bit can only be cleared by RSMRST#.

26

0h

RO

Reserved (Rsvd26)

25

0h

RW

SDX SMI Enable (SDX_​SMI_​EN)

Software sets this bit to enable SCC SMI events

24:19

0h

RO

Reserved (RSVD24_​18)

18

0h

RW

THERM SMI Enable (THERM_​SMI_​EN)

Software sets this bit to enable Thermal SMI# events.

17

0h

RW

Legacy USB 2 Enable (LEGACY_​USB2_​EN)

Enables legacy USB2 logic to cause SMI#.

16:15

0h

RO

Reserved (Rsvd)

14

0h

RW

Periodic Enable (PERIODIC_​EN)

Setting this bit will cause an SMI# to be generated when the PERIODIC_​STS bit is set in the SMI_​STS register.

13

0h

RW/L

TCO Enable (TCO_​EN)

1 = Enables the TCO logic to generate SMI#. 0 = Disables TCO logic generating an SMI#.
If the NMI2SMI_​EN bit is set, then SMI's that are caused by NMI's (i.e. rerouted) will not be gated by the TCO_​EN bit . Even if the TCO_​EN bit is 0, the NMI's will still be routed to cause the SMI#.
NOTE: This bit can not be written once the TCO_​LOCK bit (at offset 08h of TCO I/O Space) is set. This prevents unauthorized software from disabling the generation of TCO-based SMI's.

12

0h

RO

Reserved (Rsvd_​1)

11

0h

RW

MCSMI Enable (MCSMI_​EN)

Software sets this bit to 1 to enables the processor to trap access to the microcontroller range (62h or 66h). An SMI# will also be generated.

10:8

0h

RO

Reserved (Rsvd_​2)

Reserved. (since no corresponding enable bit required)

7

0h

WO

BIOS_​RLS (BIOS_​RLS)

Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. This bit always reads a zero.
NOTE: GBL_​STS being set will cause an SCI, even if the SCI_​EN bit is not set. Software must take great care not to set the BIOS_​RLS bit (which causes GBL_​STS to be set) if the SCI handler is not in place.

6

0h

RW

Software SMI Timer Enable (SWSMI_​TMR_​EN)

Software sets this bit to a 1 to start the Software SMI# Timer. When the timer expires (depending on the SWSMI_​RATE_​SEL bits), it will generate an SMI# and set the SWSMI_​TMR_​STS bit. The SWSMI_​TMR_​EN bit will remain at 1 until software sets it back to 0. Clearing the SWSMI_​TMR_​EN bit before the timer expires will reset the timer and the SMI# will not be generated. The default for this bit is 0.

5

0h

RW

APMC Enable (APMC_​EN)

If set, this enables writes to the APM_​CNT register to cause an SMI#

4

0h

RW

SMI On Sleep Enable (SMI_​ON_​SLP_​EN)

If this bit is set, an SMI# is generated when a write access attempts to set the SLP_​EN bit (in the PM1_​CNT register). Furthermore, the processor will not put the system to a sleep state. It is expected that the SMI# handler will turn off the SMI_​ON_​SLP_​EN bit before actually setting the SLP_​EN bit.

3

0h

RW

Legacy USB Enable (LEGACY_​USB_​EN)

Enables legacy USB circuit to cause SMI#.

2

0h

RW

BIOS Enable (BIOS_​EN)

Enables the generation of SMI# when ACPI software writes a 1 to the GBL_​RLS bit. Note that if the BIOS_​STS bit, which gets set when software writes a 1 to GBL_​RLS bit, is already a 1 at the time that BIOS_​EN becomes 1, an SMI# will be generated when BIOS_​EN gets set.

1

1h

RW/1S/V

End of SMI (EOS)

This bit controls the arbitration of the SMI signal. This bit must be set in order for SMI# to be asserted low after SMI# has been asserted previously. Once SMI# is asserted low, the EOS bit is automatically cleared. The SMI handler should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to reassert SMI upon detection of an SMI event and the setting of a SMI status bit. The SMI# signal will go inactive for 4 PCI clocks.

0

0h

RW/L

Global SMI Enable (GBL_​SMI_​EN)

When set, this bit enables the generation of SMIs in the system upon any enabled SMI event. This bit is reset by a PCI reset event. If this bit is not set, no SMI# will be generated.
NOTE: When the SMI_​LOCK bit is set, this bit cannot be changed.