SMI Enable (GPI_SMI_EN_GPP_D_0) – Offset 258 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD_0) Reserved
23:5	0h	RO	Reserved
4	0h	RW	GPI SMI Enable (GPI_SMI_EN_xxgpp_sd_4) Same description as bit 0.
3	0h	RW	GPI SMI Enable (GPI_SMI_EN_xxgpp_sd_3) Same description as bit 0.
2	0h	RW	GPI SMI Enable (GPI_SMI_EN_xxgpp_sd_2) Same description as bit 0.
1	0h	RW	GPI SMI Enable (GPI_SMI_EN_xxgpp_sd_1) Same description as bit 0.
0	0h	RW	GPI SMI Enable (GPI_SMI_EN_xxgpp_sd_0) This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the corresponding GPIROUTSMI must be set to '1'. 0 = disable SMI generation 1 = enable SMI generation

SMI Enable (GPI_SMI_EN_GPP_B_0) NMI Status (GPI_NMI_STS_GPP_B_0)

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