SMI Status (GPI_SMI_STS_GPP_B_0) – Offset 240 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
31:20	0h	RO	Reserved (RSVD_0) Reserved
19:15	0h	RO	Reserved
14	0h	RW/1C/V	GPI SMI Status (GPI_SMI_STS_xxgpp_sb_14) This bit is set to '1' by hardware when a level event (See RxEdCfg, RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) - The corresponding PAD_OWN[2:0] is '000' (i.e. ACPI GPIO Mode). If the following conditions are true, then an SMI will be generated if the GPI_SMI_STS bit is set: 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad's GPIROUTSMI is set Writing a value of '1' will clear the bit while writing a value of '0' has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.
13:0	0h	RO	Reserved

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0) SMI Status (GPI_SMI_STS_GPP_D_0)

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