31:24

0h

RO

Reserved (RSVD_​0)

Reserved

23:5

0h

RO

Reserved

4

0h

RW/1C/V

GPI SMI Status (GPI_​SMI_​STS_​xxgpp_​sd_​4)

Same description as bit 0.

3

0h

RW/1C/V

GPI SMI Status (GPI_​SMI_​STS_​xxgpp_​sd_​3)

Same description as bit 0.

2

0h

RW/1C/V

GPI SMI Status (GPI_​SMI_​STS_​xxgpp_​sd_​2)

Same description as bit 0.

1

0h

RW/1C/V

GPI SMI Status (GPI_​SMI_​STS_​xxgpp_​sd_​1)

Same description as bit 0.

0

0h

RW/1C/V

GPI SMI Status (GPI_​SMI_​STS_​xxgpp_​sd_​0)

This bit is set to '1' by hardware when a level event (See RxEdCfg, RxInv) is detected, and all the following conditions are true:
- The corresponding pad is used in GPIO input mode (PMode)
- The corresponding PAD_​OWN[2:0] is '000' (i.e. ACPI GPIO Mode).
If the following conditions are true, then an SMI will be generated if the GPI_​SMI_​STS bit is set:
1. The corresponding bit in the GPI_​SMI_​EN register is set
2. The corresponding pad's GPIROUTSMI is set
Writing a value of '1' will clear the bit while writing a value of '0' has no effect.

0 = There is no SMI event
1 = There is an SMI event

The state of GPI_​SMI_​EN does not prevent the setting of GPI_​SMI_​STS.
Defaults for these bits are dependent on the state of the GPI pads.