SPI BAR1 MMIO (BIOS_SPI_BAR1) – Offset e0 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
31:25	0h	RW/L	Memory BAR (MEMBAR) Software programs this register with the base address of the device's memory region. The Host/BIOS MMIO registers in the flash controller are offset from this BAR. This BAR is locked when EXT_BIOS_LOCK =1, and it's used to direct read the extended BIOS region above 16MB.
24:4	0h	RO	Memory Size (MEMSIZE) Hardwired to 0 to indicate 32MB (RTL uses parameter EXT_BIOS_SIZE) of memory space.
3	0h	RO	Prefetchable (PREFETCH) A device can mark a range as prefetchable if there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables.
2:1	0h	RO	Type (TYP) Hardwired to 0 to indicate that Base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory Space.
0	0h	RO	Memory Space Indicator (MEMSPACE) Hardwired to 0 to identify a Memory BAR.

BIOS Control (BIOS_SPI_BC) SSRAM PCI Configuration

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