31:10

0h

RO

Reserved

9:8

0h

RO/V

Current TState (CURRTSTATE)

These bits reflect the current T-state. These bits are mirrored from the PMU register. These bits also reflect the 2-bit throttle pin values that the PMC drives to other IPs 0x0 : T0 State 0x1 : T1 State 0x2 : T2 State 0x3 : T3 State

7:5

0h

RO

Reserved

4

0h

RW

SW Throttle Change (SWTHROT_​CHANGE)

SW must write this bit to 0, then 1 (edge detect) to initiate a T-state change request. The requested T-state value needs to be programmed in bits 1:0 of this register at the time of the 0->1 transition

3:2

0h

RO

Reserved

1:0

0h

RW

SW Throttle State (SWTHROTTSTATE)

0x0 : T0 State 0x1 : T1 State 0x2 : T2 State 0x3 : T3 State HW initiates a change to the targeted SWTHROT_​TSTATE upon seeing bit 4 of this register (SWTHROT_​CHANGE) change from 0 to 1. Note: Depending on other throttling modes being enabled, SW may not get its requested T-state. The deepest T-state requested by either SW, PMC or for temperature trip points being exceeded will take precedence