Target Status Register (SSTS) – Offset 10 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll the register until a write takes effect before assuming that a write has completed internally.

Bit Range	Default	Access	Field Name and Description
7:1	0h	RO	Reserved (RSVD) Reserved
0	0h	RW/1C	HOST_NOTIFY_STS (HNS) This bit is set to a 1 when a successful Host Notify Command on the SMBus pins is completely received. Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit after reading any information needed from the Notify address and data registers by writing a 1 to this bit. Note that the controller will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the controller will NACK the first byte (host address) of any new Host Notify commands on the SMBus. Writing a 0 to this bit has no effect.

Bit Range

Default

Access

Field Name and Description

7:1

Reserved (RSVD)

Reserved

RW/1C

HOST_NOTIFY_STS (HNS)

This bit is set to a 1 when a successful Host Notify Command on the SMBus pins is completely received. Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit after reading any information needed from the Notify address and data registers by writing a 1 to this bit. Note that the controller will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the controller will NACK the first byte (host address) of any new Host Notify commands on the SMBus. Writing a 0 to this bit has no effect.

Target Command Register (SCMD)

SMBUS_PIN_CTL Register (SMBC) Target Command Register (SCMD)