15:5

0h

RO

Reserved (RSVD)

Reserved

4

0h

RW/1C

SMLink SMI Status (SMLINK_​SMI_​STS)

This bit is set to 1 when it receives the SMI message (encoding 08h in the command type) on the SMLinks Interface. Software clears the bit by writing a 1 to this bit position. This bit is in the resume well. It is reset by RSMRST#, but not by the PCI Reset associated with exit from S3-S5 states. This allows the software (presumably BIOS) to get the interrupt, see this new bit set, and decidedly go into the pre-determined (by local policy) sleep state. The advantage here is that race conditions are eliminated if the bit is only meant for power-down instead of potentially being meant for power-up or power-down depending on the current state (like the real power button).

3

0h

RO

Reserved (RSVD_​1)

Reserved

2

0h

RO/V

NO_​REBOOT_​PIN_​STRAP_​STATUS (NRSTRAP_​STS)

This bit reflects the state of the No_​Reboot strap that is sampled on PWROK rise.

1

0h

RW/1C

SECOND_​TO_​STS (SECOND_​TO_​STS)

This bit is set to 1 to indicate that the TIMEOUT bit had been (or is currently) set and a second timeout occurred before the TCO_​RLD register was written. If this bit is set and the NO_​REBOOT config bit is 0, then the system will reboot after the second timeout. The reboot is done by asserting PLTRST#. This bit is only cleared by writing a 1 to this bit or by a RSMRST#.

0

0h

RW/1C

INTRD_​DET (INTRD_​DET)

Intruder Detect. Bit set to 1 to indicate that an intrusion was detected. This is latched. This bit is cleared by writing a 1 to this bit or by RTEST#. This bit is backed in the RTC Well.
Note: This bit has a recovery time. After writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 microseconds before it is read as a 0. Software must be aware of this recovery time when reading this bit after clearing it.
Note: If the INTRUDER# signal is active when the software attempts to clear the INTRD_​DET bit, the bit will remain as a 1, and the SMI# will be generated again immediately. The SMI handler can clear the INTRD_​SEL bits to avoid further SMIs. However, if the INTRUDER# signals goes inactive and then active again, there will not be further SMIs (because the INTRD_​SEL bits would select that no SMI# be generated).
If the INTRUDER# signal goes inactive some point after the INTRD_​DET bit is written as a 1, then the INTRD_​DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit.