Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
ID | Date | Version | Classification |
---|---|---|---|
834819 | 01/29/2025 | 001 | Public |
Temperature Sensor Control and Status (TSS0) – Offset 1560
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/L | Policy Lock-Down Bit (TSS0LOCK) When set to 1, this bit locks down the following fields: |
30:17 | 0h | RO | Reserved |
16 | 0h | RW/L | TS MASK for MAXTEMP calculation (TSMASKEN) 0x0 (Default): Temperature reported from TS is used for temperature comparison with PMC. 0x1: Temperature reported from the TS is masked for TEMP comparison within PMC. This in turn will also enable/disable SMI/SCI assertions for alert thermal events from this TS. |
15:10 | 0h | RO | Reserved |
9 | 0h | RO/V | TS Reading Valid (TSRV) This bit indicates if the TS die temperature reported in valid or not. |
8:0 | 0h | RO/V | TS Reading (TSR) The TS die temperature with resolution of 1oC in S9.8.0 2s complement format 0x001 positive 1oC 0x000 0oC 0x1FF negative 1oC 0x1D8 negative 40oC and so on |