Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
ID | Date | Version | Classification |
---|---|---|---|
834819 | 01/29/2025 | 001 | Public |
Thermal Alert Trip Status (TAS) – Offset 1538
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved |
15 | 0h | RW/1C/V | TS Alert High-to-Low Event (AHLE) 0x1: Indicates that an Thermal Sensor trip event occurred based on a higher to lower temperature transition thru the trip point 0x0: No trip for this event Software must write a 1 to clear this status bit Note: AHLE will not be set until there has been one occurrence of a Low to High event (ALHE must have been set once). This prevents the case where the system power up at a reasonably high temperature and starts to cool off while booting and causing an interrupt before there is SW loaded to handle it |
14:12 | 0h | RO | Reserved |
11:8 | 0h | RO/V | High-to-Low trip TS (HLTTS) 0xF 0x3 : Reserved 0x2 : TS2 0x1 : TS1 0x0 : TS0 |
7 | 0h | RW/1C/V | TS Alert Low-to-High Event (ALHE) 0x1: Indicates that an Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point 0x0: No trip for this event Software must write a 1 to clear this status bit Note: AHLE will not be set until there has been one occurrence of a Low to High event (ALHE must have been set once). This prevents the case where the system power up at a reasonably high temperature and starts to cool off while booting and causing an interrupt before there is SW loaded to handle it |
6:4 | 0h | RO | Reserved |
3:0 | 0h | RO/V | Low-to-High trip TS (LHTTS) 0xF 0x3 : Reserved 0x2 : TS2 0x1 : TS1 0x0 : TS0 |