63:32

f00000h

RO

Timer 0 Interrupt Rout (TIMER0_​INT_​ROUT_​CAP)

This 32-bit read-only field indicates to which interrupts in the 8259 or I/O (x) APIC this timers interrupt can be routed to. This is used in conjunction with the TIMERn_​INT_​ROUT_​CNF field. Writes to this field will have no effect.

Note: If interrupt is handled via 8259, only interrupts 0-15 are applicable and valid. Each bit in this field corresponds to a particular interrupt. For example, if this timers interrupt can be mapped to interrupts 16, 18, 20, 22, or 24, then bits 16, 18, 20, 22, and 24 in this field will be set to 1. All other bits will be 0.

Timer 0,1 : Bits 20, 21, 22, and 23 in this field will have a value of 1. All other bits will be 0.

Timer 2 : Bits 11, 20, 21, 22, and 23 in this field will have a value of 1. All other bits will be 0. If IRQ 11 is used, software should ensure IRQ 11 is not shared with any other devices to guarantee the proper operation of this timer.

Timer 3 : Bits 12, 20, 21, 22, and 23 in this field will have a value of 1. All other bits will be 0. If IRQ 12 is used, software should ensure IRQ 12 is not shared with any
other devices to guarantee the proper operation of this timer.

Timer 4-7: This field is always 0 as interrupts from these timers can only be delivered via direct FSB interrupt messages.

31:16

0h

RO

Reserved (RSV_​31_​16)

These bits will return 0 when read. Writes will have no effect.

15

1h

RO

FSB Interrupt Delivery Capability (TIMER0_​FSB_​INT_​DEL_​CAP)

This bit is always read as 1, since the HPET implementation supports the direct FSB interrupt delivery.

14

0h

RW

Timer 0 FSB Interrupt Delivery Enable (TIMER0_​FSB_​EN_​CNF)

When set, this will force the interrupts for Timer n to be delivered directly as FSB messages, rather than using the 8259 or I/O (x) APIC. In this case, the TIMERn_​INT_​ROUTE_​CNF field in this
register will be ignored and the TIMERn_​FSB_​ROUT register will be used instead.
Timer 0, 1, 2, 3: This bit is a read/write bit.
Timer 4, 5, 6, 7: This bit is always Read-Only 1 as interrupt from these timers can only be delivered via direct FSB interrupt messages.

13:9

0h

RW

Interrupt Route (TIMER0_​INT_​ROUT_​CNF)

This 5-bit field indicates the routing for the interrupt to the 8259 or I/O APIC. A maximum of 32 interrupts are supported. Software writes to this field to select which interrupt in the 8259 or I/O (x)APIC will be used for this timers interrupt. The default value for this register is 00h.
If the Legacy Rout bit is set, then Timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. If the TIMERn_​FSB_​EN_​CNF bit is set, then the interrupt will be delivered directly to the FSB, and this bit field has no effect.
If interrupt is handled via 8259, only interrupts 0-15 are applicable and valid. Software must not program any value other than 0-15 in this field.
Software must ensure that the value is valid for a particular timer as indicated by the TIMERn_​INT_​ROUTE_​CAP field for that timer. The HW does not check the validity of the value written.
For Timers 4-7, this field is always Read-Only 0 as interrupts from these timers can only be delivered via direct FSB interrupt messages.

8

0h

RW

Timer 0 32-bit Mode (TIMER0_​32_​MODE_​CNF)

Software can set this bit to force a 64-bit timer to behave as a 32-bit timer. This is typically needed if the software is not willing to halt the main counter to read or write a particular timer, and the software not capable of do an atomic 64-bit read to the timer.

When TIMER0_​32MODE_​CNF is set to '1', the hardware counter will essentially be doing 32-bit operation on comparator match and rollovers. I.e. the upper 32-bit of the Timer 0 Comparator Value register is ignored. The upper 32-bit of the main counter is not involved in any roll over from lower 32-bit of the main counter and becomes all zero's.

For timer 0, this bit will be read/write and default to 0. For timers 1-7, this bit will always read as 0 and writes will have no effect (since these seven timers are 32-bits).

7

0h

RO

Reserved (RSV_​7)

This bit will return 0 when read. Writes will have no effect.

6

0h

WO

Timer 0 Value Set (TIMER0_​VAL_​SET_​CNF)

Software uses this bit only for timers that have been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly set the timers accumulator. Software does NOT have to write this bit back to 0 (it automatically clears). This bit will return 0 when read.

Software should not write a 1 to this bit position if the timer is set to non-periodic mode.

Writes will only have an effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1-7 as they do not support the periodic mode.

5

1h

RO

Timer 0 Size (TIMER0_​SIZE_​CAP)

Read-only Indicator of the timers size capability.
1: 64-bits
0: 32-bits.
The value is 1 (64-bits) for timer 0, and 0 (32-bits) for timers 1-7.

4

1h

RO

Periodic Interrupt Capable (TIMER0_​PER_​INT_​CAP)

If this read-only bit is 1, then the hardware supports a periodic mode for this timers interrupt.
The value is 1 (periodic supported) for timer 0, and 0 (not supported) for timers 1-7.

3

0h

RW

Timer 0 Type (TIMER0_​TYPE_​CNF)

Setting this bit to 1 enables the timer to generate a periodic interrupt if it is capable of doing so. If the TIMERn_​PER_​INT_​CAP bit is 0, then this bit will always return 0 when read and writes will have no impact.
For timer 0, this bit will be read/write, with default of 0. For timers 1-7, this bit will be read-only, with a fixed value of 0.

2

0h

RW

Timer 0 Interrupt Enable (TIMER0_​INT_​ENB_​CNF)

This bit must be set to 1 to enable timer n to cause an interrupt when it times out. If this bit is 0, the timer can still count and generate appropriate status bits, but will not cause an interrupt. Default value is 0.

1

0h

RW

Timer Interrupt Type (TIMER0_​INT_​TYPE_​CNF)

Determines whether an edge or level interrupt will be used for this timer (when enabled).
0: Edge-triggered. If another interrupt occurs, another edge will be generated.
1: Level-triggered. The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt Status Register. If another interrupt occurs before the interrupt is cleared, the interrupt will remain active.
The default value is 0, edge-triggered. The interrupt type for any timer should be set before that timer generates any interrupts. If the interrupt type is changed dynamically, there will be some delay before the new type takes effect. That delay is not specified.
Timer 0-3: This bit is a read/write bit as both edge and level triggered modes are supported.
Timer 4-7: This bit is always Read-Only 0 as only edge-triggered mode is supported.

0

0h

RO

Reserved (RSV_​0)

These bits will return 0 when read. Writes will have no effect.