Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1) – Offset c8 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

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Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

ID	Date	Version	Classification
834819	01/29/2025	001	Public

Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1) – Offset c8

The fields in this register pertain to cycles targeting addresses outside of Component 0. The lockable bits in this register are locked when either CPPTV is set to '1' by hardware or when VCL is '1'.

Bit Range	Default	Access	Field Name and Description
31	0h	RO/V	Component Property Parameter Table Valid (CPPTV) This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter Table in Component 1. Note: If this bit is set software must not overwrite bits that were initialized by hardware via SFDP discovery.
30	0h	RO	Reserved (RSVD_30)
29	0h	RW/V/L	64k Erase Valid (EO_64K_VALID) 0: The EO_64k opcode is not valid. 1: The EO_64k opcode is valid.
28	0h	RW/V/L	4k Erase Valid (EO_4K_VALID) 0 The EO_4k opcode is not valid. 1 The EO_4k opcode is valid.
27	0h	RW/L	RPMC Supported (RPMC_SUPPORTED) 0: The device does not support RPMC. 1: The device supports RPMC.
26	0h	RW/V/L	Deep Powerdown Supported (DEEP_PWRDN_SUPPORTED) 0: The device does not support Deep Powerdown. 1: The device supports Deep Powerdown.
25	0h	RW/V/L	Suspend/Resume Supported (SUSPEND_RESUME_SUPPORTED) 1: The device does not support Suspend/Resume. 0: The device supports Suspend/Resume.
24	0h	RW/V/L	Soft Reset Supported (SOFT_RST_SUPPORTED) 0: The device does not support Soft Reset. 1: The device supports Soft Reset.
23:16	0h	RW/V/L	64k Erase Opcode (EO_64K) This register is programmed with the Flash 64k sector erase instruction opcode for component 1. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit.
15:8	20h	RW/V/L	4k Erase Opcode (EO_4K) This register is programmed with the Flash 4k subsector erase instruction opcode for component 1. Software must program this register if the SFDP table for this component does not show 4 kByte erase capability. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit.
7:5	0h	RW/V/L	Quad Enable Requirements (QER) See description in SFDP0_VSCC0.QER.
4	0h	RW/V/L	Write Enable on Write Status (WEWS) See description in SFDP0_VSCC0.WEWS.
3	0h	RW/V/L	Write Status Required (WSR) See description in SFDP0_VSCC0.WSR.
2	0h	RW/V/L	Write Granularity (WG) See description in SFDP0_VSCC0.WG.
1:0	0h	RW/L	Reserved (RSVD_1_0)