Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_0) – Offset 790 - 001 - ID:819324 | Intel® Core™ Ultra Processors for Edge (PS Series) SOC I/O Registers

Intel® Core™ Ultra Processors for Edge (PS Series) SOC I/O Registers

ID	Date	Version	Classification
819324	04/02/2024	001	Public

Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_0) – Offset 790

Bit Range	Default	Access	Field Name and Description
31:30	1h	RW	Pad Reset Config (PADRSTCFG) This register controls which reset is used to reset GPIO pad register fields in various GPIO registers (PADCFGLOCK, PADCFGLOCKTX, GPI_IS, GPI_IE, GPI_GPE_STS, GPI_GPE_EN, GPI_SMI_STS, SPI_SMI_EN, GPI_NMI_STS, GPI_NMI_EN, PAD_CFG_DW0, and PAD_CFG_DW1). 00 = RSMRST# 01 = Host deep reset. This reset occurs when any of the following occur: Host reset (with or without power cycle) is initiated, Global reset is initiated, or Deep Sx entry. This reset does NOT occur as part of S3/S4/S5 entry. 10 = PLTRST# 11 = Global Reset
29	0h	RW	RX Pad State Select (RXPADSTSEL) Determine from which node the RX pad state for native function should be source from. This field only affects the pad state value being fanned out to native function(s) and is not meaningful if the pad is in GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Syncronized Internal RX pad state (subject to RXINV , hardware debouncer (if any) and PreGfRXSel settings) \t\t\t
28	0h	RW	RX Raw Override to '1' (RXRAW1) This bit determines if the selected pad state is being overridden to '1'. This field only makes sense when the buffer is configured as an input in either GPIO Mode or native function mode. The override takes place at the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally \t\t\t
27	0h	RO	Reserved
26:25	2h	RW	RX Level/Edge Configuration (RXEVCFG) Determine if the internal RX pad state (RXPadStSel=1) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to GPIORXState or native functions) but how the interrupt or wake triggering events should be delivered to the GPIO Community Controller. 0h = Level 1h = Edge 2h = Disable 3h = Either rising edge or failing edge \t\t\t
24	0h	RW	Pre Glitch Filter Stage RX Pad State Select (PREGFRXSEL) Determine if the synchronized version of the raw RX pad state should be subjected to glitch filter or not. This field only makes sense when the RX buffer is configured as an input and is not disabled. 0 = Select synchronized, non filtered RX pad state 1 = Select synchronized, filtered RX pad state The selected RX pad state can be further subjected to polarity inversion through RXINV \t\t\t
23	0h	RW	RX Invert (RXINV) This bit determines if the selected pad state should go through the polarity inversion stage. This field only makes sense when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion \t\t\t
22:21	0h	RW	RX/TX Enable Config (RXTXENCFG) This controls the RX and TX buffer enables for the function selected by Pad Mode, but is not applicable when Pad Mode is 0 (i.e. GPIO mode). Hardware shall ensure GPIOTxDis and GPIORxDis are controlling the RX and TX buffers when this field is 0 and Pad Mode is 0. 0 = Function defined in Pad Mode controls TX and RX Enables 1 = Function controls TX Enable and RX Disabled with RX drive 0 internally 2 = Function controls TX Enable and RX Disabled with RX drive 1 internally 3 = Function controls TX Enabled and RX is always enabled \t\t\t
20	0h	RW	GPIO Input Route IOxAPIC (GPIROUTIOXAPIC) Determine if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause peripheral IRQ 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s). \t\t\t
19	0h	RW	GPIO Input Route SCI (GPIROUTSCI) Determine if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause SCI 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s)
18	0h	RW	GPIO Input Route SMI (GPIROUTSMI) Determine if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause SMI. 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). \t\t\t
17	0h	RW	GPIO Input Route NMI (GPIROUTNMI) Determine if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 1 = Routing can cause NMI. Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. \t\t\t
16:13	0h	RO	Reserved
12:10	0h	RW	Pad Mode (PMODE) This field determines whether the Pad is controlled by GPIO controller or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad 1h = Function 1, if applicable, control the Pad ... 15 = Function 15, if applicable, control the Pad Default value is determined by the default functionality of the pad.
9	1h	RW	GPIO RX Disable (GPIORXDIS) RX buffer enable control when PMode = 0 ONLY. No effect when the pad in native mode. 0 = Enable the input buffer (active low enable) of the pad 1 = Disable the input buffer of the pad. Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.
8	1h	RW	GPIO TX Disable (GPIOTXDIS) TX buffer enable control when PMode = 0 ONLY. No effect when the pad in native mode. 0 = Enable the output buffer (active low enable) of the pad 1 = Disable the output buffer of the pad; i.e. Hi-Z
7:2	0h	RO	Reserved
1		RO/V	GPIO RX State (GPIORXSTATE) This is the current internal RX pad state after Glitch Filter logic stage and is not affected by PMode and RXINV, hardware debouncer (if any) settings. When read, this bit returns a 0 if GPIORxDis is 1. \t\t\t
0	0h	RW	GPIO TX State (GPIOTXSTATE) TX state in when PMode = 0 ONLY. No effect when the pad in native mode. 0 = Drive a level '0' to the TX output pad 1 = Drive a level '1' to the TX output pad \t\t\t