Ingredients

• Software Tools: Intel® System Debugger NDA

• Debug Probe: Intel® Silicon View Technology (Intel® SVT) Closed Chassis Adapter (CCA) or Intel® SVT Debug Class (DbC) USB Debug Cable

• Hardware: Whiskey Lake U platform running TianoCore EDK II BIOS with Intel® Direct Connect Interface (Intel® DCI) debug interfaces enabled.

  Important:

  This recipe also demonstrates source-level debugging using the Intel® Serial IO UART Driver. For this step, it is necessary to have the BIOS build tree including the sources and symbols. The same instructions can also be applied for debugging issues in kernel drivers.

Connect Intel® System Debugger to the Target

Follow instructions to connect to the target. Ensure that a target connection has been successfully established.

Boot to EFI Shell

Once the target connection is fully established, do the following:

1. Create a debug configuration.

2. Select one of the CPU threads in the Debug view and halt execution using the CPU run-control buttons available in the Eclipse* toolbar.

3. To view the various PCI devices and their configuration, open the PCI Devices view (Windows > Show View > PCI Devices).

   

4. Select the device to be analyzed from the drop-down list of PCI devices. Use the refresh button if needed.

   For this recipe we are using the UART controller located on the Cannon Point PCH.Identify the UART controller based on its Bus:Device.Function (BDF) identifier. BDF of PCI devices are specified in the External Design Specification (EDS).

   

The PCI device viewer displays device configuration as shown in the image above. The PCI address domain consists of three distinct address spaces:

• Configuration

• Memory

• I/O space.

Each peripheral device contains a set of well-defined configuration registers in its PCI configuration space. These registers are used not only to identify devices but also to supply device configuration information. For example, Base Address Registers (BAR) in the device configuration space must be mapped before a device can respond to data access. System firmware assigns regions of memory space in the PCI address domain to PCI peripherals. The base address of a region is stored in the BAR. Device addresses in memory space are memory-mapped into the host address domain so that data access to any device can be performed by the processor’s native load or store instructions.

For the UART controller in the figure above, the BAR0 holds the system memory base address of the controller assigned by the Intel Serial IO UART Driver during the PCI device initialization phase. You can find the details of this UART controller in the External Design Specification (EDS) Volume 2 for Canon Lake PCH, which is available at Resource & Documentation Center. According to EDS, various device registers including the Receive Buffer Register (RBR), Transmit Holding Register (THR), and others are memory-mapped with the base address in the BAR0. You can view these device registers by mapping the contents of the BAR0 in the Memory view. Refer to the instructions how to view the memory contents.

Watchpoints feature available in Intel® System Debugger – System Debug can be used to halt the execution of the CPU when any of these device registers are modified. For example, setup a watchpoint at the base address (0xfe036000) listed under BAR0 and resume the cores. The cores will be halted again when they access the UART device register mapped to address 0xfe036000.

Once the cores are halted, use the Load available debug symbols function to load the source code. Path mapping may be necessary if the BIOS was not built on the same host where the debugger is running. Follow the instructions on manual symbol loading.

In this example, the cores were halted when the Intel Serial IO UART Driver checked the status of the UART buffers. The variable SerialRegisterBase used to access the UART registers points to the address in the BAR0. You can confirm this by checking the value of this variable listed in the Variables view.

Troubleshooting

Issue

Failed to connect to target

Solution

• Firmware: Firmware running on the target must be configured to enable CCA interface.

• BIOS: BIOS must be configured to enable CCA/DbC interface. For more information, refer to the BIOS user guide or Intel System Debugger User Guide: Target Setup.

For additional help, refer to the platform documentation, primary Troubleshooting chapter, or contact your Intel presentative. Priority support is available for Intel System Debugger NDA users through Online Service Center or Intel® Premier Support.