Last Branch Record (LBR) execution trace for Lakemont / MinuteIA cores in Simics® simulation.

Enabled Ponte Vecchio tracing support for Intel® Graphics System Controller (Intel® GSC) and Intel® Chassis System Controller (Intel® CSC).

Earlyboot: Show current trace cycle in Python* status bar.

TraceCLI: Added target_​status command to provide information about the currently configured target.

Added warning message when using latest software, but FPGA programming is outdated.

Show progress information while ongoing connection establishment.

Fixed reset toolbar commands for Simics® simulation connection.

Fixed possible hang if there is no probe connected while ongoing connection establishment.

Fixed conditions of IO access breakpoints. This fix enabled breaking on BIOS POST code changes.

Proper display of power loss in the Debug view.

Fixed some filtering issues in the Symbol Browser.

Fixed incorrect app_​sgpio_​dir_​ctrl (0x46) FPGA register programming.

Fixed misleading error message verbiage “Error in serial communication while writing: Access is denied”.

Fixed GUI sorting by multiple columns lasts performance issue.

Fixed incorrect sending trigger config for disabled channels.

Fixed IDV Tool hang when platform.json was changed and saved during capture.

Fixed issue with rules order was always re-sorted by content in the first column after a save.