Intel® System Debugger User Guide
Set Up Target
Configure the target platform BIOS settings and FIT/mFIT settings described in the Platform Closed Chassis Debug User Guide. Sign in to Resource & Documentation Center and search by document number, 626623 for all platforms before Meteor Lake and 730814 for Meteor Lake. Refer to the Troubleshooting section for instructions on troubleshooting target connection issues. If further support is required, contact your BIOS vendor, or your Intel support to get further guidance.
Common Configuration
To enable a target for debugging and tracing, the associated BIOS configuration must be applied. The following instructions are generic and might not completely match your setup. If available, follow the target specific instructions first.
These are examples of options and possible configurations, not all of them can be applied to your target. If an option is available, choose the value that fits best.
Check if your target BIOS provides any of the following menus:
Intel Advanced Menu > Debug Settings
Platform Configuration > PCH-IO Configuration > Debug Settings
Enable Intel® Direct Connect Interface (Intel® DCI): search for a Intel® DCI enable or Platform Debug Consent option and configure it according to your connection method.
Intel® DCI is the communication layer for USB JTAG debugging required for the following connection methods:
Intel® Silicon View Technology (Intel® SVT) DbC USB Debug Cable
Intel® DCI OOB via Intel® SVT Closed Chassis Adapter (CCA)
Intel® DCI OOB via Intel® SVT Closed Chassis Adapter (CCA) + 2-wire adapter
To use these methods, verify that the Intel® DCI driver is installed. It should happen automatically during Intel® System Debugger installation.
Enable debugging of your target: enable CPU Run Control options in your BIOS settings to use System Debug and WinDbg features.
Enable System Trace (if required and supported) to trace your target execution: search for Trace Hub or North Peak, or NPK options and enable them. This enables Intel® Trace Hub (Intel® TH) and firmware trace sources.