Intel® System Debugger User Guide

ID 648476
Date 06/13/2024
Confidential
Document Table of Contents
Document Table of Contents
Intel(R) System Debugger NDA Get Started Version History Supported Platforms and Probes Virtual UART over Intel® DCI Platform Provisioning Learn More about Debug Probes and Technologies Host Operating Systems Get Help Trainings System Debug System Trace Crash Log Intel(R) Debug Extensions for WinDbg* Intelligent Debug & Validation Tool (IDV Tool) Command Line Interface (CLI) Reference Troubleshooting Samples Cookbook Target Indicator Lauterbach TRACE32* Software Support Debugging Zephyr* Applications with Intel® System Debugger Notices and Disclaimers
Intel(R) System Debugger NDA
Get Started
Get Started Set Up Target Connect your Target Launch Intel® System Debugger Custom Installation
Set Up Target
Connect your Target
Connect your Target Physical Target Virtual Target (Simics® Simulator) Remote Target
Physical Target
Virtual Target (Simics® Simulator)
Remote Target
Launch Intel® System Debugger
Launch Intel® System Debugger Manual Configuration Additional Configuration Options
Manual Configuration
Additional Configuration Options
Custom Installation
Version History
Version History Intel® System Debugger 2024 NDA Update 2422 Intel® System Debugger 2024 NDA Update 2418 Intel® System Debugger 2024 NDA Update 2414 Intel® System Debugger 2024 NDA Update 2410 Intel® System Debugger 2024 NDA Update 2406 Intel® System Debugger 2023 NDA Update 2350 Intel® System Debugger 2023 NDA Update 2346 Intel® System Debugger 2023 NDA Update 2342 Intel® System Debugger 2023 NDA Update 2338 Intel® System Debugger 2023 NDA Update 2334 Intel® System Debugger 2023 NDA Update 2330 Intel® System Debugger 2023 NDA Update 2326 Intel® System Debugger 2023 NDA Update 2322 Intel® System Debugger 2023 NDA Update 2318 Intel® System Debugger 2023 NDA Update 2314 Intel® System Debugger 2023 NDA Update 2310 Intel® System Debugger 2023 NDA Update 2306 Intel® System Debugger 2022 NDA Update 2250 Intel® System Debugger 2022 NDA Update 2246 Intel® System Debugger 2022 NDA Update 2238 Intel® System Debugger 2022 NDA Update 2234 Intel® System Debugger 2022 NDA Update 2230 Intel® System Debugger 2022 NDA Update 2226 Intel® System Debugger 2022 NDA Update 2222 Intel® System Debugger 2022 NDA Update 2214 Intel® System Debugger 2022 NDA Update 2210 Intel® System Debugger 2022 NDA Update 2206
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Intel® System Debugger 2022 NDA Update 2214
Intel® System Debugger 2022 NDA Update 2210
Intel® System Debugger 2022 NDA Update 2206
Supported Platforms and Probes
Virtual UART over Intel® DCI
Virtual UART over Intel® DCI Virtual UART Usage COM Port Interface for Virtual UART
Virtual UART Usage
COM Port Interface for Virtual UART
Platform Provisioning
Platform Provisioning Debug Token Configuration Debug Token usage in UI Debug Token usage CLI Offline Debug Token creation using Flash Programming Tool (FPT) Debug Token creation and Firmware upload using Intel® DnX On-Target Debug Token Management
Debug Token Configuration
Debug Token usage in UI
Debug Token usage CLI
Offline Debug Token creation using Flash Programming Tool (FPT)
Debug Token creation and Firmware upload using Intel® DnX
On-Target Debug Token Management
Learn More about Debug Probes and Technologies
Host Operating Systems
Get Help
Trainings
System Debug
System Debug Before You Begin Setup System Debug JTAG Debugging Specifics Debugging Basics Advanced Debugging Scenarios Debugging UEFI BIOS Debugging Linux* Kernels Debugging System Management Mode Debugging the Virtual Target Simulation Debugging Intel(R) Trusted Domain Extention (Intel(R) TDX) Debugging coreboot* Scripting Samples User Interface Reference
Before You Begin
Before You Begin Recommended Compiler Flags
Recommended Compiler Flags
Setup System Debug
Setup System Debug Change System Debug Configuration Disconnecting from the Debugger
Change System Debug Configuration
Disconnecting from the Debugger
JTAG Debugging Specifics
Debugging Basics
Debugging Basics Target Run Control Loading Debug Information Using Breakpoints Viewing and Modifying Registers Working with Memory Collecting Execution Trace Perf Collector Tool
Target Run Control
Target Run Control CPU Operation Modes Filter Hardware Threads
CPU Operation Modes
Filter Hardware Threads
Loading Debug Information
Loading Debug Information Prerequisite: File Path Mapping Manual Loading Automatic Loading Loading BIOS ROM File Using Map Files
Prerequisite: File Path Mapping
Manual Loading
Automatic Loading
Loading BIOS ROM File
Using Map Files
Using Breakpoints
Using Breakpoints Breakpoint Status Indicators Setting a Breakpoint on a Line or Function Setting a Breakpoint on an Instruction Address Setting Watchpoints Setting Platform Breaks Setting the IO Port Access Breakpoint Setting a Breakpoint at Module Entry Setting Breakpoint Conditions
Breakpoint Status Indicators
Setting a Breakpoint on a Line or Function
Setting a Breakpoint on an Instruction Address
Setting Watchpoints
Setting Platform Breaks
Setting the IO Port Access Breakpoint
Setting a Breakpoint at Module Entry
Setting Breakpoint Conditions
Viewing and Modifying Registers
Viewing and Modifying Registers Architectural Registers Platform Registers
Architectural Registers
Platform Registers
Working with Memory
Collecting Execution Trace
Perf Collector Tool
Advanced Debugging Scenarios
Advanced Debugging Scenarios Executing External Python* Scripts Automating Tasks on Launch Customizing the Loading of Debug Information Configure Call Stack
Executing External Python* Scripts
Automating Tasks on Launch
Customizing the Loading of Debug Information
Configure Call Stack
Debugging UEFI BIOS
Debugging UEFI BIOS Loading Pre-EFI Initialization Modules (PEIMs) Loading EFI Images for DXE Phase and Onwards Loading the Modules of an EFI Firmware Volume (FV) Breaking on POST Codes
Loading Pre-EFI Initialization Modules (PEIMs)
Loading EFI Images for DXE Phase and Onwards
Loading the Modules of an EFI Firmware Volume (FV)
Breaking on POST Codes
Debugging Linux* Kernels
Debugging Linux* Kernels Loading a KASLR-Enabled Linux* Kernel Manual Loading of a Linux* Kernel Loading Linux* Kernel Modules Loading Individual Modules Break at the Initialization of a Linux* Kernel Module
Loading a KASLR-Enabled Linux* Kernel
Manual Loading of a Linux* Kernel
Loading Linux* Kernel Modules
Loading Individual Modules
Break at the Initialization of a Linux* Kernel Module
Debugging System Management Mode
Debugging System Management Mode Breaking on SMM Entry Accessing the SMRAM State Save Map
Breaking on SMM Entry
Accessing the SMRAM State Save Map
Debugging the Virtual Target Simulation
Debugging the Virtual Target Simulation Connect to the Virtual Target Debugging Capabilities
Connect to the Virtual Target
Debugging Capabilities
Debugging Intel(R) Trusted Domain Extention (Intel(R) TDX)
Debugging Intel(R) Trusted Domain Extention (Intel(R) TDX) Breaking on SEAM Entry Breaking on TDCall
Breaking on SEAM Entry
Breaking on TDCall
Debugging coreboot*
Scripting Samples
Scripting Samples Creating Simple Commands for Frequent Debug Tasks Executing Multiple Steps in a Row Configuring the Scan for Debug Information Configuring the Scan for EFI Images Load Debug Information for All Threads Reading and Writing IO Ports Break at the Initialization of a Linux* Kernel Module Create the history of commands
Creating Simple Commands for Frequent Debug Tasks
Executing Multiple Steps in a Row
Configuring the Scan for Debug Information
Configuring the Scan for EFI Images
Load Debug Information for All Threads
Reading and Writing IO Ports
Break at the Initialization of a Linux* Kernel Module
Create the history of commands
User Interface Reference
User Interface Reference Drag and Drop Views
Drag and Drop
Views
Views Breakpoints View Debug View Disassembly View Expressions View Global Descriptor Table View Interrupt Descriptor Table View Instruction Trace View I/O Port View Local Descriptor Table View Memory Browser View Modules View Model-specific registers View Page Tables View PCI Devices View Platform Register Dictionary View Platform Register Editor View Platform Register Watch View Registers View ISD Shell View Variables View
Breakpoints View
Debug View
Disassembly View
Expressions View
Global Descriptor Table View
Interrupt Descriptor Table View
Instruction Trace View
I/O Port View
Local Descriptor Table View
Memory Browser View
Modules View
Model-specific registers View
Page Tables View
PCI Devices View
Platform Register Dictionary View
Platform Register Editor View
Platform Register Watch View
Registers View
ISD Shell View
Variables View
System Trace
System Trace Before You Begin Setup System Trace Capture Trace File Types in System Trace Import Pre-captured Trace File Analyze Trace Export Data Linux kernel tracing Appendix A: Setting Up Hardware Appendix B: Tracing with Simics(R) Simulator On Target Trace: Capture trace capture directly on device under test Managing catalogs using Catalog Service Switch to High Bandwidth USB transport with Trace Profile Appendix Z: Trace Message View Legacy
Before You Begin
Setup System Trace
Capture Trace
Capture Trace Start Trace Capture Stop Capturing Trace
Start Trace Capture
Start Trace Capture Advanced: Capture Trace without Changing Hardware Configuration
Advanced: Capture Trace without Changing Hardware Configuration
Stop Capturing Trace
File Types in System Trace
Import Pre-captured Trace File
Import Pre-captured Trace File Import Trace Extension
Import Trace Extension
Analyze Trace
Analyze Trace Trace Message Viewer Filter or Search Visualize Trace via Timeline Viewer Analyze Discontinuous Trace Advanced Trace Analysis Trace Analysis: Hints
Trace Message Viewer
Trace Message Viewer Message Viewer Column Timeline Viewer
Message Viewer
Column
Timeline Viewer
Filter or Search
Filter or Search Quick Filter Or Search Rules View
Quick Filter Or Search
Rules View
Visualize Trace via Timeline Viewer
Visualize Trace via Timeline Viewer Overview Create a Timeline Definition File Edit a Timeline Definition File Timeline Viewer
Overview
Create a Timeline Definition File
Edit a Timeline Definition File
Timeline Viewer
Analyze Discontinuous Trace
Advanced Trace Analysis
Advanced Trace Analysis Master/Channel Filtering Trace Capture File Size Limit Decode Part of a File Decode Trace with a Different Decode Network Enable Low Voltage Margining Overrides Controlling Power Managment for Intel(R) Trace Hub (Intel(R) TH)
Master/Channel Filtering
Trace Capture File Size Limit
Decode Part of a File
Decode Trace with a Different Decode Network
Enable Low Voltage Margining Overrides
Controlling Power Managment for Intel(R) Trace Hub (Intel(R) TH)
Trace Analysis: Hints
Trace Analysis: Hints Copying and Pasting Trace Entries Drag and Drop to Import Files Changing the Timestamp Format Sorting Files in the Project Explorer
Copying and Pasting Trace Entries
Drag and Drop to Import Files
Changing the Timestamp Format
Sorting Files in the Project Explorer
Export Data
Export Data Export Intel(R) Trace Hub Binary for Intel(R) Flash Image Tool (Intel(R) FIT)
Export Intel(R) Trace Hub Binary for Intel(R) Flash Image Tool (Intel(R) FIT)
Linux kernel tracing
Appendix A: Setting Up Hardware
Appendix A: Setting Up Hardware Ice Lake - Integrated Sensor Hub Skylake PCH-H and Skylake PCH-LP Broxton P Gordon Peak Modular Reference Board (GP MRB)
Ice Lake - Integrated Sensor Hub
Skylake PCH-H and Skylake PCH-LP
Broxton P
Gordon Peak Modular Reference Board (GP MRB)
Appendix B: Tracing with Simics(R) Simulator
Appendix B: Tracing with Simics(R) Simulator Configure Simics(R) Simulator Configure and Enable Trace
Configure Simics(R) Simulator
Configure and Enable Trace
On Target Trace: Capture trace capture directly on device under test
Managing catalogs using Catalog Service
Switch to High Bandwidth USB transport with Trace Profile
Appendix Z: Trace Message View Legacy
Appendix Z: Trace Message View Legacy Analyze Trace Messages with Message View Analyze Message Distribution
Analyze Trace Messages with Message View
Analyze Trace Messages with Message View Decode the Summary Message with Trace Extension Show the Source of Traces Select Trace Fields to Be Displayed Mark Trace Messages Export Trace Messages to CSV
Decode the Summary Message with Trace Extension
Show the Source of Traces
Select Trace Fields to Be Displayed
Mark Trace Messages
Export Trace Messages to CSV
Analyze Message Distribution
Crash Log
Crash Log Intel(R) Crash Log Framework Intel(R) Crash Log Framework Graphical User Interface
Intel(R) Crash Log Framework
Intel(R) Crash Log Framework Graphical User Interface
Intel(R) Debug Extensions for WinDbg*
Intel(R) Debug Extensions for WinDbg* Get Started Using Intel(R) Debug Extensions for WinDbg* over Intel(R) Direct Connect Interface Intel(R) Debug Extensions for WinDbg* for Intel(R) Processor Trace (Intel(R) PT) Debugging Advanced Configuration and Power Interface (ACPI) WinDbg* Support for Microsoft* Hyper-V WinDbg* Support for pre-NT applications Intel(R) Debug Extensions for WinDbg* for Source Level Debugging WinDbg* Support for RegDB WinDbg* Support for Peripheral Component Interconnect (PCI) Buses Debugging the Virtual Target Simulation with Intel(R) Debug Extensions for WinDbg* Remote HW debugging with Intel(R) Debug Extensions for WinDbg* Appendix: Establishing Concurrent Debug Sessions
Get Started
Get Started Launch Intel(R) Debug Extensions for WinDbg* Target Connection Using Intel(R) Debug Extensions for WinDbg* with WinDbg* Preview
Launch Intel(R) Debug Extensions for WinDbg*
Target Connection
Using Intel(R) Debug Extensions for WinDbg* with WinDbg* Preview
Using Intel(R) Debug Extensions for WinDbg* over Intel(R) Direct Connect Interface
Using Intel(R) Debug Extensions for WinDbg* over Intel(R) Direct Connect Interface Setting Low Voltage Margining Mode Target Run Control Setting Breakpoints Performing Full Memory Dump Performing Raw Memory Dump Collecting Stop Information Collecting and analyzing BERT file
Setting Low Voltage Margining Mode
Target Run Control
Setting Breakpoints
Performing Full Memory Dump
Performing Raw Memory Dump
Collecting Stop Information
Collecting and analyzing BERT file
Intel(R) Debug Extensions for WinDbg* for Intel(R) Processor Trace (Intel(R) PT)
Intel(R) Debug Extensions for WinDbg* for Intel(R) Processor Trace (Intel(R) PT) Requirements and Constrains Loading the Intel(R) Debug Extensions for WinDbg* for Intel(R) Processor Trace (Intel(R) PT) Commands Using the Extension
Requirements and Constrains
Loading the Intel(R) Debug Extensions for WinDbg* for Intel(R) Processor Trace (Intel(R) PT)
Commands
Commands Displaying the Current Configuration Enabling and Disabling Tracing Output Configuration IP Filter Configuration Timestamps Extension Commands for Decoding Intel(R) Processor Trace
Displaying the Current Configuration
Enabling and Disabling Tracing
Output Configuration
IP Filter Configuration
Timestamps
Extension Commands for Decoding Intel(R) Processor Trace
Using the Extension
Using the Extension Reserving Memory on the Target for Trace Data Configuring a Trace Region in Memory Tracing a Windows* Kernel Function Reconstructing Program Execution Flow
Reserving Memory on the Target for Trace Data
Configuring a Trace Region in Memory
Tracing a Windows* Kernel Function
Reconstructing Program Execution Flow
Debugging Advanced Configuration and Power Interface (ACPI)
Debugging Advanced Configuration and Power Interface (ACPI) Before You Begin Supported ACPI Extensions Debugging Use Cases
Before You Begin
Supported ACPI Extensions
Supported ACPI Extensions !amli set !amli dns !amli find !amli u !amli lc !amli r !amli dl !acpicache !acpiinf !acpiirqarb !amli dh !facs !fadt !mapic !nsobj !nstree !rsdt
!amli set
!amli dns
!amli find
!amli u
!amli lc
!amli r
!amli dl
!acpicache
!acpiinf
!acpiirqarb
!amli dh
!facs
!fadt
!mapic
!nsobj
!nstree
!rsdt
Debugging Use Cases
Debugging Use Cases Investigating a Frozen System Tracing ACPI BIOS Code
Investigating a Frozen System
Tracing ACPI BIOS Code
WinDbg* Support for Microsoft* Hyper-V
WinDbg* Support for Microsoft* Hyper-V Introducing Microsoft* Hyper-V Setting Up the Extension Virtual Machine Architecture Virtual Machine Extension (VMX) operation VMM Software Lifecycle VMX Instructions for Intel(R) 64 and IA-32 Architectures
Introducing Microsoft* Hyper-V
Setting Up the Extension
Virtual Machine Architecture
Virtual Machine Extension (VMX) operation
VMM Software Lifecycle
VMM Software Lifecycle VMX Operation Restrictions Address Translation in VMX Operation
VMX Operation Restrictions
Address Translation in VMX Operation
VMX Instructions for Intel(R) 64 and IA-32 Architectures
VMX Instructions for Intel(R) 64 and IA-32 Architectures Instructions for Managing the Intel(R) Virtual Machine Control Structure Shadowing (Intel(R) VMCS Shadowing) Instructions for Managing the VMX Operation Instructions for Managing the VMX-specific Translation Lookaside Buffer (TLB) Instructions for Using the Guest Software
Instructions for Managing the Intel(R) Virtual Machine Control Structure Shadowing (Intel(R) VMCS Shadowing)
Instructions for Managing the VMX Operation
Instructions for Managing the VMX-specific Translation Lookaside Buffer (TLB)
Instructions for Using the Guest Software
WinDbg* Support for pre-NT applications
Intel(R) Debug Extensions for WinDbg* for Source Level Debugging
Intel(R) Debug Extensions for WinDbg* for Source Level Debugging Setting Up Windbg For Source Level Debugging Debug Operations For Source Level Debugging
Setting Up Windbg For Source Level Debugging
Debug Operations For Source Level Debugging
WinDbg* Support for RegDB
WinDbg* Support for Peripheral Component Interconnect (PCI) Buses
Debugging the Virtual Target Simulation with Intel(R) Debug Extensions for WinDbg*
Remote HW debugging with Intel(R) Debug Extensions for WinDbg*
Appendix: Establishing Concurrent Debug Sessions
Intelligent Debug & Validation Tool (IDV Tool)
Intelligent Debug & Validation Tool (IDV Tool) IDV Tool Hardware Overview Before You Begin Get Started Capture Signals Analyze Captured Signals
IDV Tool Hardware Overview
Before You Begin
Get Started
Get Started Use Existing Rule Kit
Use Existing Rule Kit
Capture Signals
Analyze Captured Signals
Analyze Captured Signals Use Timeline Viewer Create Rules
Use Timeline Viewer
Create Rules
Command Line Interface (CLI) Reference
Command Line Interface (CLI) Reference Intel(R) System Debugger - System Debug CLI User Guide Intel(R) System Debugger - TraceCLI User Guide Intel(R) System Debugger - System Trace - Target Agent User Guide IPC CLI Documentation Python* API Reference
Intel(R) System Debugger - System Debug CLI User Guide
Intel(R) System Debugger - System Debug CLI User Guide Notices and Disclaimers
Notices and Disclaimers
Intel(R) System Debugger - TraceCLI User Guide
Intel(R) System Debugger - TraceCLI User Guide TraceAPI intel_systrace TraceCLI Settings Custom Python* Environment EarlyBoot TraceCLI Live output commands Notices and Disclaimers
TraceAPI
intel_systrace
TraceCLI Settings
Custom Python* Environment
EarlyBoot
TraceCLI Live output commands
Notices and Disclaimers
Intel(R) System Debugger - System Trace - Target Agent User Guide
Intel(R) System Debugger - System Trace - Target Agent User Guide Quick Start Trace Agent CLI
Quick Start
Trace Agent CLI
IPC CLI Documentation
IPC CLI Documentation DAL-CLI to IPC-CLI Migration Global Commands ippcli device commands Device Actions Device Configs ippcli Devices and Nodes JTAG and I2C Locking IPC API Breaks and Breakpoints Events Diagnostics Dynamic Initialization IPC Datatypes for Users Settings Acknowledgements All Commands
DAL-CLI to IPC-CLI Migration
Global Commands
ippcli device commands
Device Actions
Device Configs
ippcli Devices and Nodes
JTAG and I2C Locking
IPC API Breaks and Breakpoints
Events
Diagnostics
Dynamic Initialization
IPC Datatypes for Users
Settings
Acknowledgements
All Commands
Python* API Reference
Troubleshooting
Troubleshooting Automatic Status Report Check Debug Connection with System Configuration Checker Issues and Solutions
Automatic Status Report
Check Debug Connection with System Configuration Checker
Issues and Solutions
Issues and Solutions Target Run Control Issues Target Simulation Issues System Debug Issues System Trace Issues Intel® Debug Extensions for WinDbg Issues
Target Run Control Issues
Target Simulation Issues
System Debug Issues
System Trace Issues
Intel® Debug Extensions for WinDbg Issues
Samples
Samples EFI Application System Debug Usage Sample System Trace Usage Sample Intel® Debug Extensions for WinDbg Usage Sample
EFI Application
EFI Application Build and flash to a USB drive EFI Application on Windows* Build and flash to a USB drive EFI Application on Linux*
Build and flash to a USB drive EFI Application on Windows*
Build and flash to a USB drive EFI Application on Windows* Install EDK II Build the EFI Sample Application Flashing the EFI Application to a USB drive
Install EDK II
Build the EFI Sample Application
Flashing the EFI Application to a USB drive
Build and flash to a USB drive EFI Application on Linux*
Build and flash to a USB drive EFI Application on Linux* Install EDK II Build the EFI Application sample Writing the EFI Application to an USB drive
Install EDK II
Build the EFI Application sample
Writing the EFI Application to an USB drive
System Debug Usage Sample
System Trace Usage Sample
Intel® Debug Extensions for WinDbg Usage Sample
Cookbook
Cookbook Debug System Management Mode (SMM) Debug PCI Device Capture and Decode Early-boot Intel® Converged Security and Management Engine (Intel® CSME) Traces in a Cold Boot Scenario
Debug System Management Mode (SMM)
Debug PCI Device
Capture and Decode Early-boot Intel® Converged Security and Management Engine (Intel® CSME) Traces in a Cold Boot Scenario
Target Indicator
Target Indicator Launching the Target Indicator Target Indicator States
Launching the Target Indicator
Target Indicator States
Lauterbach TRACE32* Software Support
Lauterbach TRACE32* Software Support Prerequisites Determine the Required Version of the Lauterbach TRACE32* Software Download the Lauterbach TRACE32 Debugger Verify the Download Version Install the Lauterbach TRACE32 Debugger Verify Lauterbach TRACE32 Integration
Prerequisites
Determine the Required Version of the Lauterbach TRACE32* Software
Download the Lauterbach TRACE32 Debugger
Verify the Download Version
Install the Lauterbach TRACE32 Debugger
Verify Lauterbach TRACE32 Integration
Debugging Zephyr* Applications with Intel® System Debugger
Debugging Zephyr* Applications with Intel® System Debugger Prerequisites Configure Eclipse* IDE Set up Intel® System Debugger Workspace Create a Project Build the Project Debug Zephyr* Application Finish Debug Session Appendix: Set up Intel® Programmable Services Engine in Intel® System Debugger Workspace Troubleshooting
Prerequisites
Configure Eclipse* IDE
Configure Eclipse* IDE Install Intel® System Debugger Install Eclipse* Plug-in for Zephyr* Project
Install Intel® System Debugger
Install Eclipse* Plug-in for Zephyr* Project
Set up Intel® System Debugger Workspace
Create a Project
Create a Project Importing a Project
Importing a Project
Build the Project
Debug Zephyr* Application
Debug Zephyr* Application Prepare the Target Perform Basic Debugging Tasks
Prepare the Target
Perform Basic Debugging Tasks
Finish Debug Session
Appendix: Set up Intel® Programmable Services Engine in Intel® System Debugger Workspace
Troubleshooting
Notices and Disclaimers
Intel(R) System Debugger NDA
Get Started
Version History
Supported Platforms and Probes
Virtual UART over Intel® DCI
Platform Provisioning
Learn More about Debug Probes and Technologies
Host Operating Systems
Get Help
Trainings
System Debug
System Trace
Crash Log
Intel(R) Debug Extensions for WinDbg*
Intelligent Debug & Validation Tool (IDV Tool)
Command Line Interface (CLI) Reference
Troubleshooting
Samples
Cookbook
Target Indicator
Lauterbach TRACE32* Software Support
Debugging Zephyr* Applications with Intel® System Debugger
Notices and Disclaimers

Supported Platforms and Probes

Each Intel® System Debugger tool supports its own set of platforms and probes. The following probes are commonly used for connection:

  • Intel® In-Target Probe (Intel® ITP) - XDP3

    ITP-XDP3 in the table.

  • Intel® Direct Connect Interface (Intel® DCI) Out of Band (OOB) via Intel® Silicon View Technology (Intel® SVT) Closed Chassis Adapter (CCA).

    CCA (DCI OOB) in the table

  • Intel® DCI 2-wire via Intel® SVT Closed Chassis Adapter (CCA).

    CCA (DCI 2-wire) in the table.

  • Intel® SVT Debug Class (DbC) USB Debug Cable.

    DbC in the table.

  • Intel® DCI OOB via Intel® SVT Closed Chassis Adapter (CCA) + Intel® DCI USB Debug Class (DbC). This method suggests simultaneous use of a DbC cable and a CCA adapter.

    CCA + DbC in the table.

  • Simics® simulator – virtual target simulation.

See also:

Learn More about Debug Probes and Technologies

Debug and Trace

The table below provides an overview of target/probe combinations supported by System Debug and System Trace components of the Intel® System Debugger NDA in the present release.

Note:

The core count of the target platform component does not affect connection and debugging experience. If you face any issues, refer to the Known Issues section of Release Notes or contact Customer Support.

Target Components

Connection Methods: System Debug

Connection Methods: System Trace

Ash Creek Falls CPU / Lewisburg PCH

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Alder Lake CPU / Alder Lake PCH-N

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI 2-wire), DbC

Alder Lake CPU / Alder Lake PCH-P

ITP-XDP3, CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Alder Lake CPU / Alder Lake PCH-S

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI 2-wire), DbC, Simics® simulator

Arctic Sound GPU

Simics® simulator

Lauterbach* MIPI60 probe

Arrow Lake CPU / Meteor Lake PCH-S

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

Broxton I SOC (Apollo Lake)

DbC, Simics® simulator

DbC

Broxton P SOC (Apollo Lake)

DbC, Simics® simulator

DbC

Broxton P SOC: Gordon Peak Modular Reference Board (GP MRB)

DbC, Simics® simulator

DbC

Cannon Lake CPU / Cannon Point PCH-LP

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Cascade Lake CPU / Kaby Lake PCH-H (Glacier Falls)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Cascade Lake CPU / Lewisburg PCH (Purley Refresh)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Coffee Lake CPU / Cannon Point PCH-H

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Coffee Lake CPU / Kaby Lake PCH-H

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Coffee Lake CPU / Cannon Point PCH-LP

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Comet Lake CPU / Comet Lake PCH-H

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Comet Lake CPU / Cannon Point PCH-H

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Comet Lake CPU / Comet Lake PCH-V

CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Comet Lake CPU / Tiger Lake PCH-H (Rocket Lake S)

ITP-XDP3, CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Comet Lake CPU / Comet Lake PCH-LP

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Cooper Lake CPU / Lewisburg PCH (Cedar Island)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Denverton SOC (Car Branch 1, Car Branch 2, Denverton)

DbC, Simics® simulator

DbC

DG1 PCI Express Card GPU

Simics® simulator

Lauterbach* MIPI60 probe

DG2 PCI Express Card GPU

Simics® simulator

Lauterbach* MIPI60 probe

Diamond Rapids CPU

Simics® simulator

Simics® simulator

Elkhart Lake CPU / Mule Creek Canyon PCH

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Emerald Rapids CPU / Emmitsburg PCH (Eagle Stream Refresh)

ITP-XDP3, CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

Gemini Lake SOC

DbC, Simics® simulator

DbC

Gemini Lake Refresh SOC (Gemini Lake +)

DbC, Simics® simulator

Grand Ridge CPU / Emmitsburg PCH

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

Granite Rapids CPU

ITP-XDP3, Simics® simulator

ITP-XDP3, Simics® simulator

Granite Rapids D (Kaseyville) CPU

ITP-XDP3, Simics® simulator

ITP-XDP3, Simics® simulator

Ice Lake CPU / Cedar Fork PCH

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Ice Lake CPU / Lewisburg PCH (Whitley)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Ice Lake CPU / Ice Lake PCH-LP

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Ice Lake CPU / Ice Lake PCH-N

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Jasper Lake CPU / Jasper Lake PCH-N (Jasper Lake +)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Kaby Lake CPU / Kaby Lake PCH-H

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Kaby Lake CPU / Sunrise Point PCH-H

ITP-XDP3, CCA (DCI OOB), Simics® simulator

CCA (DCI OOB)

Kaby Lake CPU / Sunrise Point PCH-LP

CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Lakefield SOC

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Lunar Lake CPU / Lunar Lake SoC M

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

Meteor Lake CPU / Meteor Lake PCH-S

ITP-XDP3, CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI 2-wire), DbC, Simics® simulator

Raptor Lake CPU / Alder Lake PCH-S

ITP-XDP3, CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

Rocket Lake CPU / Comet Lake PCH-H

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Rocket Lake CPU / Tiger Lake PCH-H (Tatlow)

ITP-XDP3, CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Sapphire Rapids CPU / Alder Lake PCH-S (Fishhawk Falls)

ITP-XDP3, CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

Sapphire Rapids CPU / Emmitsburg PCH (Eagle Stream)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC, Simics® simulator

Sierra Forest CPU

ITP-XDP3, Simics® simulator

ITP-XDP3, Simics® simulator

Sierra Forest CPU / Emmitsburg PCH

ITP-XDP3, Simics® simulator

ITP-XDP3, Simics® simulator

Skylake CPU / Sunrise Point PCH-H

ITP-XDP3, CCA (DCI OOB), Simics® simulator

CCA (DCI OOB)

Skylake Server CPU / Kaby Lake PCH-H (Basin Falls)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Skylake Server CPU / Lewisburg PCH (Anderson Creek, Purley)

ITP-XDP3, CCA (DCI OOB), CCA+DbC, DbC, Simics® simulator

CCA (DCI OOB), CCA+DbC, DbC

Skylake CPU / Comet Lake PCH-LP

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

Skylake CPU / Sunrise Point PCH-LP

ITP-XDP3, CCA (DCI OOB), Simics® simulator

CCA (DCI OOB)

Snow Ridge CPU / Cedar Fork PCH (Jacobsville)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Spring Hill CPU / Ice Lake PCH-LP

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC

Tiger Lake CPU / Tiger Lake PCH-H

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

Tiger Lake CPU / Tiger Lake PCH-LP

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

CCA (DCI OOB), CCA (DCI 2-wire), DbC, Simics® simulator

Whiskey Lake CPU / Comet Lake PCH-LP

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Whiskey Lake CPU / Cannon Point PCH-LP

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Whiskey Lake CPU / Sunrise Point PCH-LP (Amber Lake Y 4+2)

ITP-XDP3, CCA (DCI OOB), DbC, Simics® simulator

CCA (DCI OOB), DbC

Ponte Vecchio (PVC) PCI Express Card GPU

Lauterbach* MIPI60 probe

Battlemage

Lauterbach* MIPI60 probe, Simics® simulator

Panther Lake

Simics® simulator

Simics® simulator

Nova Lake

Simics® simulator

Clearwater Forest

Simics® simulator

Simics® simulator

Granite Rapids Workstation (Meteor Lake PCH)

Simics® simulator

Simics® simulator

Wildcat Lake

Simics® simulator

Simics® simulator

Crash Log

Intel® System Debugger - Crash Log supports the following target components in the present release:

  • Alder Lake CPU (variants: H, K, L, M, N, P, R, S)

  • Alder Lake PCH (variants: N, P, S)

  • Arrow Lake (variants: P, S)

  • Broxton I, Broxton P

  • Comet Lake PCH (variants: H, LP)

  • Cannon Lake (variants: H, LP)

  • Emmitsburg PCH

  • Emerald Rapids (variants: SP)

  • Granite Rapids (variants: AP, SP)

  • Granite Rapids-D

  • Ice Lake CPU (variants: H, I, S3, S4, UN/YN)

  • Ice Lake PCH (variants: H, LP, N)

  • Jasper Lake CPU

  • Jasper Lake PCH

  • Lakefield CPU (base die and compute die)

  • Lunar Lake (variants: M)

  • Meteor Lake CPU

  • Meteor Lake PCH

  • Mule Creek Canyon PCH

  • Raptor Lake (variants: P, S, U)

  • Rocket Lake (variants: S, U)

  • Sapphire Rapids SP

  • Sapphire Rapids HBM

  • Sierra Forest (variants: SP, AP)

  • Tiger Lake CPU (variants: H, R, S, UN/YN)

  • Tiger Lake PCH (variants, H, K, LP)

Virtual UART over Intel® DCI