VMX Operation Restrictions

In a VMX operation, processors may fix certain bits in CR0 and CR4 to specific values and not support other values. Thus, if any of these bits contain an unsupported value, the VMXON instruction fails. Any attempt to set one of these bits to an unsupported value while in VMX operation (including VMX root operation) using any of the CLTS, LMSW, or MOV CR instructions causes a general- protection exception. VM entry or VM exit cannot set any of these bits to an unsupported value.

The first processors to support VMX operation require that the following bits be 1 in VMX operation:

CR0.PE
CR0.NE
CR0.PG
CR4.VMXE

Note:

The restrictions on CR0.PE and CR0.PG imply that VMX operation is supported only in the paged protected mode (including IA-32e mode). Therefore, guest software cannot be run in the unpaged protected mode or in the real-address mode.

Future processors might require a different amount of memory to be reserved. In this case, the VMX capability-reporting mechanism reports this change to the software.

Address Translation in VMX Operation

VMM Software Lifecycle Address Translation in VMX Operation