31

1h

RW

D3 Hot function enable register (D3_​HOT_​FXN_​EN)

This bit is from pin input which is set 1. But we allow software to alter it if it is needed.
1: D3 hot enabled
0: D3 hot not abled.

30

0h

RW

Allow L1 Core Clock Gating (ALL_​L1_​CORE_​CG)

When set to 1 allows core clock being gated during L1 state.

29

0h

RW

Allow Engine PHY Status Extension (AL_​EP_​SEXT)

When set to 1 allows the engine to extend PHY status of PCIe PIPE for one more cycle. This is due to the fact that our rate change function has a potential of not being able to sample the phystatus signal.

28

0h

RW

Allow Engine PCIe Rate Change Passing (ALL_​EP_​RCP)

When set to 1 allows the engine to pass PCIe rate change signal as it is from PCIe core to PCIe PHY.

27

0h

RW

Allow Engine PERST Fundamental Reset (AL_​PERST_​FRST)

When set to 1 allow engine to treat PERST# as a foundamental reset

26

0h

RW

Overwrite PCIe P2 to P1 (OVR_​PCIE_​P2_​P1)

When set to 1 will overwrite a PCIe powerdown state of P2 to P1.

25:23

0h

RO

Reserved

22

0h

RW

RESERVED (RSVD_​1)

RESERVED

21

0h

RW

Force save_​restore 1 (FORCE_​SR1)

When set to 1, it will force the save_​restore flag to 1. This flag is an bit to ensure that we have masked the update during low power state. If software write this bit to 1, it must write it to 0 in order to resume the normal save and restore function.

20:18

0h

RO

Reserved

17

0h

RW

cfg_​dis_​arc_​RXDP3 (CFG_​DIS_​ARC_​RXDP3)

When set to '1' DIsables arc to RXDET_​p3 on disc from U2P3/U3

16

0h

RW

cfg clk gate dis (CCGD)

1: Disable USB3 port clock gating
0: Enable USB3 port clock gating

15:13

0h

RO

Reserved

12

1h

RW

Enable Host Engine Generate PME (EN_​HE_​GEN_​PME)

This is a global switch to whether or not eable this host engine to generate PME message.

11

1h

RW

Enable Isolation (EN_​ISOL)

When set to '1' enable isolation

10

0h

RO

Reserved

9

0h

RW

Enable Core Clock Gating (EN_​CORE_​CG)

When set to '1' disable core clock gating based on low power state entered

8

0h

RW

Enable PHY Status Timeout (EN_​PHY_​STS_​TO)

When set to '1' enable PHY status timeout function which is designed to cover the PCIePHY issue that we may have not able to detect the PHY status toggle.

7

1h

RW

Ignore aux_​pm_​en PCIe Core (IGN_​APE_​PC)

When set to '1' ignore the aux_​pm_​en reg from PCIe core to continue the remote wake/clock switching support

6

1h

RW

Enable P2 Overwrite P1 (EN_​P2_​OVR_​P1)

When set to '1' enable P2 overwrite P1 when PCIe core has indicated the transition from P0 to P1. This is to enable entering the even lower power state.

5

1h

RW

Enable P2 Remote Wake (EN_​P2_​REM_​WAKE)

When set 1 '1' enable the remote wake function by allowing P2 clock/switching and P2 entering

4:1

0h

RW

Forced PM State (FORCED_​PM_​STATE)

Forced PM state

0

0h

RW

Initiate Force PM State (INIT_​FPMS)

When set to '1' force PM state to go to the state indicated in bit 4:1