Catastrophic Trip Point Enable (CTEN) – Offset 150c - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

This register is used to enable Catastrophic Trip point assertion into S5 state on a Cattrip event. This bit should always be set in all functional cases.

Bit Range	Default	Access	Field Name and Description
31	0h	RW/L	Policy Lock-Down Bit (CTENLOCK) When written to 1, this bit prevents any more writes to this register.
30:1	0h	RO	Reserved
0	1h	RW/L	Catastrophic Power-Down Enable (CPDEN) 0x1 (Default): When set , the power management logic (PMC) transitions to the S5 state when a catastrophic temperature is detected by any of the sensor. The transition to the S5 state must be unconditional (like the Power Button Override Function). 0x0 : Disable going into S5 state on a CatTrip detection. This bit should only be set to 0 for debug purposes. Note: Thermal sensor and response logic are in the main power well; therefore, detection of a catastrophic temperature is limited to times when this well is powered and out of reset.

Bit Range

Default

Access

Field Name and Description

RW/L

Policy Lock-Down Bit (CTENLOCK)

When written to 1, this bit prevents any more writes to this register.

30:1

Reserved

RW/L

Catastrophic Power-Down Enable (CPDEN)

0x1 (Default): When set , the power management logic (PMC) transitions to the S5 state when a catastrophic temperature is detected by any of the sensor. The transition to the S5 state must be unconditional (like the Power Button Override Function).
0x0 : Disable going into S5 state on a CatTrip detection. This bit should only be set to 0 for debug purposes.
Note: Thermal sensor and response logic are in the main power well; therefore, detection of a catastrophic temperature is limited to times when this well is powered and out of reset.

EC Thermal Sensor Reporting Enable (ECRPTEN)

Max Temperature (MAX_TEMP) EC Thermal Sensor Reporting Enable (ECRPTEN)