Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795262 | 12/14/2023 | 001 | Public |
High Speed Configuration 2 (HSCFG2_MMIO) – Offset 86a4
Dummy register, mirror of physical register as HSCFG2
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:19 | 0h | RO | Rsvd1 (RSVD1) Rsvd1 |
| 18 | 0h | RW | PORT1 Host Mode Override (PORT1_HOST_MODE_OVERRIDE) When set, this bit causes the Host_Device mux on port 1 to be forced into the Host mode. |
| 17:16 | 0h | RW | eUSB2SEL (EUSB2SEL) The two bits are associate with USB2 ports 1 - bit 16 and 2 - bit 2 |
| 15 | 0h | RW | HS ASYNC Active IN Mask (HSAAIM) Determines if the Async Active will mask/ignore IN EP s. |
| 14 | 0h | RW | HS OUT ASYNC Active Polling EP Mask (HSOAAPEPM) Determines if the Async Active for OUT HS/FS/LS masks/ignores EP s that are polling/PINGing (HS) due to NAK. |
| 13 | 0h | RW | HS IN ASYNC Active Polling EP Mask (HSIAAPEPM) Determines if the Async Active for IN HS/FS/LS masks/ignores EP s that are polling due to NAK. |
| 12:0 | 0h | RO | Reserved |