Interrupt Information Byte 1 (INTRB1) – Offset 3d - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

Bit Range	Default	Access	Field Name and Description
7:0	1h	RO/V	Interrupt Pin (IPIN) Indicates the interrupt pin driven by the root port. At reset, this register takes on the following values, which reflect the reset state of the STRPFUSECFG.PxIP field: Port Bits[15:12] Bits[11:08] 1 0h STRPFUSECFG.P1IP 2 0h STRPFUSECFG.P2IP 3 0h STRPFUSECFG.P3IP : : X 0h STRPFUSECFG.PxIP The value that is programmed into STRPFUSECFG.PxIP is always reflected in this register. For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register returns a value of 00h when read, else this register returns the value from the table above. Note: Depending on the platform, the number of Root Ports supported may vary. In this case, the encodings defined in this register will be scaled accordingly.

Bit Range

Default

Access

Field Name and Description

7:0

RO/V

Interrupt Pin (IPIN)

Indicates the interrupt pin driven by the root port. At reset, this register takes on the following values, which reflect the reset state of the STRPFUSECFG.PxIP field:

Port Bits[15:12] Bits[11:08]

1 0h STRPFUSECFG.P1IP

2 0h STRPFUSECFG.P2IP

3 0h STRPFUSECFG.P3IP

:

:

X 0h STRPFUSECFG.PxIP

The value that is programmed into STRPFUSECFG.PxIP is always reflected in this register.

For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register returns a value of 00h when read, else this register returns the value from the table above.

Note: Depending on the platform, the number of Root Ports supported may vary. In this case, the encodings defined in this register will be scaled accordingly.

Bridge Control (BCTRL)

Interrupt Information Byte 0 (INTRB0) Bridge Control (BCTRL)