Message Signaled Interrupt Message Upper Address (MUA) – Offset 88 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

This is the Message Signaled Interrupt Message Upper Address registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	Upper Address (UADDR) System-specified message upper address. This register is implemented only if the Function supports a 64- bit message address (bit 7 in Message Control register Set). This register is required for PCI Express Endpoints and is optional for other Function types. If the Message Enable bit (bit 0 of the Message Control register) is Set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register

Bit Range

Default

Access

Field Name and Description

31:0

Upper Address (UADDR)

System-specified message upper

address.

This register is implemented only if the Function supports a 64-

bit message address (bit 7 in Message Control register Set).

This register is required for PCI Express Endpoints and is

optional for other Function types.

If the Message Enable bit (bit 0 of the Message Control register)

is Set, the contents of this register (if non-zero) specify the

upper 32-bits of a 64-bit message address (Address[63:32]). If

the contents of this register are zero, the Function uses the 32

bit address specified by the Message Address register

Message Signaled Interrupt Message Data (MD)

Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Data (MD)