PCI Status (PCISTS) – Offset 6 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

Bit Range	Default	Access	Field Name and Description
15	0h	RW/1C	Detected Parity Error (DPE) This register bit is set when parity error is detected.
14	0h	RW/1C	Signaled System Error (SSE) This register will set when PCICMD.SEE bit and PCISTS.DPE bit is set
13	0h	RO	Received Master-Abort Status (RMA) This bit is reserved
12	0h	RO	Received Target-Abort Status (RTA) This bit is reserved
11	0h	RW/1C	Signaled Target-Abort Status (STA) This bit must be set whenever P2SB terminates a transaction with Target-Abort
10:9	0h	RO	DEVSEL Timing (DEVSELT) These bits are reserved
8	0h	RO	Master Data Parity (MDP) This bit is reserved
7	0h	RO	Fast Back-to-Back Capable (FBC) This bit is reserved
6	0h	RO	Reserved
5	0h	RO	66MHz-Capable (MHC) This bit is reserved
4	0h	RW/O	Capabilites List (CL) 1 indicate the presence of a capabilities list. ?0? indicate that the capabilities list does not exist
3	0h	RO	Interrupt Status (ISS) This bit is reserved
2:0	0h	RO	Reserved

PCI Command (PCICMD) PCI Header Type (PCIHTYPE)