31:24

0h

RO

VC Arbitration Table Offset (VCATO)

Indicates the location of the VC Arbitration Table.



This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the MFVC Capability structure. A value of 00h indicates that the table is not present.

23:8

0h

RO

Reserved

7:0

0h

RO

VC Arbitration Capability (VCAC)

Indicates the types of VC Arbitration supported by the device for the LPVC group. This field is valid for all devices that report a Low Priority Extended VC Count greater than 0.



Each bit location within this field corresponds to a VC Arbitration Capability defined below. When more than 1 bit in this field is Set, it indicates that the device can be configured to provide different VC arbitration services.



Defined bit positions are:

Bit 0 Hardware fixed arbitration scheme, e.g., Round Robin

Bit 1 Weighted Round Robin (WRR) arbitration with 32 phases

Bit 2 WRR arbitration with 64 phases

Bit 3 WRR arbitration with 128 phases

Bits 4-7 Reserved