Power Management Capabilities (PM_CAP_MMIO) – Offset 8672 - 001 - ID:795262 | Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

Dummy register, mirror of physical register as PM_CAP. Normally, this register is read-only to report capabilities to the power management software. In order to report different power management capabilities depending on the system, the write access to this register is controlled by the Access Control bit (ACCTRL). The value written to this register does not affect the hardware other than changing the value returned during a read.
This register is modified and maintained by BIOS

Bit Range	Default	Access	Field Name and Description
15:11	18h	RW/L	PME Support (PME_SUPPORT) This 5-bit field indicates the power states in which the function may assert PME#. D1 or D2 state is not supported. For all other states, the XHC is capable of generating PME#. Software should never need to modify this field.
10	0h	RW/L	D2 Support (D2_SUPPORT) The D2 state is not supported.
9	0h	RW/L	D1 Support (D1_SUPPORT) The D1 state is not supported.
8:6	7h	RW/L	Aux Current (AUX_CURRENT) Reports 375mA maximum Suspend well current required when in the D3cold state. This value can be written by BIOS when a more accurate value is known.
5	0h	RW/L	Device Specific Initialization (DSI) Reports 0, indicating that no device-specific initialization is required.
4	0h	RO	Reserved (RSVD) Reserved
3	0h	RW/L	PME Clock (PMECLOCK) Reports 0, indicating that no PCI clock is required to generate PME#.
2:0	3h	RW/L	Version Indication (VERSION) Reports 010, indicating that it complies with Revision 1.1 of the PCI Power Management Specification.

Power Management Control/Status (PM_CS_MMIO)

Next Item Pointer 1 (PM_NEXT_MMIO) Power Management Control/Status (PM_CS_MMIO)