Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers

ID Date Version Classification
795262 12/14/2023 001 Public
Document Table of Contents
Document Table of Contents
Introduction P2SB PCI Configuration PCI Express* (PCIe*) Configuration (D1:F0) PCI Express* (PCIe*) Configuration (D6:F2) PCI Express* (PCIe*)Configuration (D6:F1) PMC I/O PMC MMIO PMC PCI Configuration SSRAM PCI Configuration USB Type-C Subsystem-PCI Root Port Configuration (D7:F0/F1/F2/F3) USB xHCI MMIO USB xHCI PCI Configuration
Introduction
P2SB PCI Configuration
P2SB PCI Configuration PCI Identifier (PCIID) PCI Command (PCICMD) PCI Status (PCISTS) PCI Header Type (PCIHTYPE) Sideband Register Access BAR (SBREG_BAR) Sideband Register BAR High DWORD (SBREG_BARH) PCI Subsystem Identifiers (PCIHSS) PCI Capabilities Pointer (CAPPTR) High Performance Event Timer Configuration (HPTC) IOxAPIC Configuration (IOAC) IOxAPIC Bus:Device:Function (IBDF) HPET Bus:Device:Function (HBDF) PCI Express Capability List Register (EXPCAPLST) PCI Express Capabilities Register (EXPCAP) Device Capabilities Register (DEVCAP) Device Control Register (DEVCTL) Device Status Register (DEVSTS) Link Capabilities Register (LNKCAP) Link Control Register (LNKCTL) Link Status Register (LNKSTS) SBI Address (SBIADDR) SBI Data (SBIDATA) SBI Status (SBISTAT) SBI Routing Identification (SBIRID) SBI Extended Address (SBIEXTADDR) P2SB Control (P2SBC) Power Control Enable (PCE) Unsupported Request Error Status (URES) Unsupported Request Error Control (UREC) Sideband Register Posted 0 (SBREGPOSTED0) Sideband Register Posted 1 (SBREGPOSTED1) Sideband Register Posted 2 (SBREGPOSTED2) Sideband Register Posted 3 (SBREGPOSTED3) Sideband Register Posted 4 (SBREGPOSTED4) Sideband Register Posted 5 (SBREGPOSTED5) Sideband Register Posted 6 (SBREGPOSTED6) Sideband Register Posted 7 (SBREGPOSTED7) Endpoint Mask 0 (EPMASK0) Endpoint Mask 1 (EPMASK1) Endpoint Mask 2 (EPMASK2) Endpoint Mask 3 (EPMASK3) Endpoint Mask 4 (EPMASK4) Endpoint Mask 5 (EPMASK5) Endpoint Mask 6 (EPMASK6) Endpoint Mask 7 (EPMASK7) MASKLOCK Control (MASKLOCK)
PCI Identifier (PCIID)
PCI Command (PCICMD)
PCI Status (PCISTS)
PCI Header Type (PCIHTYPE)
Sideband Register Access BAR (SBREG_BAR)
Sideband Register BAR High DWORD (SBREG_BARH)
PCI Subsystem Identifiers (PCIHSS)
PCI Capabilities Pointer (CAPPTR)
High Performance Event Timer Configuration (HPTC)
IOxAPIC Configuration (IOAC)
IOxAPIC Bus:Device:Function (IBDF)
HPET Bus:Device:Function (HBDF)
PCI Express Capability List Register (EXPCAPLST)
PCI Express Capabilities Register (EXPCAP)
Device Capabilities Register (DEVCAP)
Device Control Register (DEVCTL)
Device Status Register (DEVSTS)
Link Capabilities Register (LNKCAP)
Link Control Register (LNKCTL)
Link Status Register (LNKSTS)
SBI Address (SBIADDR)
SBI Data (SBIDATA)
SBI Status (SBISTAT)
SBI Routing Identification (SBIRID)
SBI Extended Address (SBIEXTADDR)
P2SB Control (P2SBC)
Power Control Enable (PCE)
Unsupported Request Error Status (URES)
Unsupported Request Error Control (UREC)
Sideband Register Posted 0 (SBREGPOSTED0)
Sideband Register Posted 1 (SBREGPOSTED1)
Sideband Register Posted 2 (SBREGPOSTED2)
Sideband Register Posted 3 (SBREGPOSTED3)
Sideband Register Posted 4 (SBREGPOSTED4)
Sideband Register Posted 5 (SBREGPOSTED5)
Sideband Register Posted 6 (SBREGPOSTED6)
Sideband Register Posted 7 (SBREGPOSTED7)
Endpoint Mask 0 (EPMASK0)
Endpoint Mask 1 (EPMASK1)
Endpoint Mask 2 (EPMASK2)
Endpoint Mask 3 (EPMASK3)
Endpoint Mask 4 (EPMASK4)
Endpoint Mask 5 (EPMASK5)
Endpoint Mask 6 (EPMASK6)
Endpoint Mask 7 (EPMASK7)
MASKLOCK Control (MASKLOCK)
PCI Express* (PCIe*) Configuration (D1:F0)
PCI Express* (PCIe*) Configuration (D1:F0) PCIE Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL)
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
PCI Express* (PCIe*) Configuration (D6:F2)
PCI Express* (PCIe*) Configuration (D6:F2) PCIE Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL)
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
PCI Express* (PCIe*)Configuration (D6:F1)
PCI Express* (PCIe*)Configuration (D6:F1) PCIE Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL)
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
PMC I/O
PMC I/O Power Management 1 Enables and Status (PM1_EN_STS) Power Management 1 Control (PM1_CNT) Power Management 1 Timer (PM1_TMR) Therm Timer Delay Register (THERM_TIMER_DELAY) SMI Control and Enable (SMI_EN) SMI Status Register (SMI_STS) General Purpose Event Control (GPE_CTRL) PM2a Control Block (PM2A_CNT_BLK) Over-Clocking WDT Control (OC_WDT_CTL) General Purpose Event 0 Status [31:0] (GPE0_STS_31_0) General Purpose Event 0 Status [63:32] (GPE0_STS_63_32) General Purpose Event 0 Status [95:64] (GPE0_STS_95_64) General Purpose Event 0 Status [127:96] (GPE0_STS_127_96) General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0) General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32) General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64) General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
Power Management 1 Enables and Status (PM1_EN_STS)
Power Management 1 Control (PM1_CNT)
Power Management 1 Timer (PM1_TMR)
Therm Timer Delay Register (THERM_TIMER_DELAY)
SMI Control and Enable (SMI_EN)
SMI Status Register (SMI_STS)
General Purpose Event Control (GPE_CTRL)
PM2a Control Block (PM2A_CNT_BLK)
Over-Clocking WDT Control (OC_WDT_CTL)
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)
General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)
General Purpose Event 0 Status [127:96] (GPE0_STS_127_96)
General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)
General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)
General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)
General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
PMC MMIO
PMC MMIO General PM Configuration A (GEN_PMCON_A) General PM Configuration B (GEN_PMCON_B) Configured Revision ID (CRID) SET STRAP MSG LOCK (SSML) SET STRAP MSG CONTROL (SSMC) SET STRAP MSG DATA (SSMD) Configured Revision ID (CRID_UIP) SLP S0 DEBUG REG0 (SLP_S0_DBG_0) SLP S0 DEBUG REG1 (SLP_S0_DBG_1) SLP S0 DEBUG REG2 (SLP_S0_DBG_2) HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1) HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6) EXT FET RAMP CFG (EXT_FET_RAMP_CFG) VCCIN AUX CONFIG Register (VCCIN_AUX_CFG) Always Running Timer Value 31:0 (ARTV_31_0) Always Running Timer Value 63:32 (ARTV_63_32) Timed GPIO Control 0 (TGPIOCTL0) Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32) Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0) Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0) Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32) Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0) Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32) Timed GPIO Control 1 (TGPIOCTL1) Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32) Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0) Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0) Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32) Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0) Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32) Min Temperature (MIN_TEMP) Max Temperature (MAX_TEMP) Catastrophic Trip Point Enable (CTEN) EC Thermal Sensor Reporting Enable (ECRPTEN) Throttle Level (TL) Thermal Sensor Alert High Value (TSAHV) Thermal Sensor Alert Low Value (TSALV) Thermal Alert Trip Status (TAS) Processor Hot Level Control (PHLC) Temperature Sensor Control and Status (TSS0) Low Power Mode Enable (LPM_EN) Wake Alarm Device Timer: AC (WADT_AC) Wake Alarm Device Timer: DC (WADT_DC) Wake Alarm Device Expired Timer: AC (WADT_EXP_AC) Wake Alarm Device Expired Timer: DC (WADT_EXP_DC) Power and Reset Status (PRSTS) Power Management Configuration Reg 1 (PM_CFG) S3 Power Gating Policies (S3_PWRGATE_POL) S4 Power Gating Policies (S4_PWRGATE_POL) S5 Power Gating Policies (S5_PWRGATE_POL) DeepSx Configuration (DSX_CFG) Power Management Configuration Reg 2 (PM_CFG2) Power Management Configuration Reg 3 (PM_CFG3) CPU Early Power-on Configuration (CPU_EPOC) ACPI Timer Control (ACPI_TMR_CTL) Last TSC Alarm Value[31:0] (TSC_ALARM_LO) Last TSC Alarm Value[63:32] (TSC_ALARM_HI) GPIO Configuration (GPIO_CFG) Host Partition Reset Causes (HPR_CAUSE0) Latency Limit Residency 0 (LAT_LIM_RES_0) Latency Limit Residency 1 (LAT_LIM_RES_1) Latency Limit Residency 2 (LAT_LIM_RES_2) SLP_S0 Residency (SLP_S0_RESIDENCY) Latency Limit Control (LATENCY_LIMIT_CONTROL) Chipset Initialization Register 1B1C (CPPMVRIC) Chipset initialization 1B4C (CPPMVRIC2) ACPI Control (ACTL) S0 Residency (S0_RES) PGD PG_ACK Status Register 0 (PPASR0) PGD PG_ACK Status Register 1 (PPASR1) PGD PFET Enable Ack Status Register 0 (PPFEAR0) PGD PFET Enable Ack Status Register 1 (PPFEAR1) PGD PG_REQ Status Register 0 (PPRSR0) PGD PG_REQ Status Register 1 (PPRSR1)
General PM Configuration A (GEN_PMCON_A)
General PM Configuration B (GEN_PMCON_B)
Configured Revision ID (CRID)
SET STRAP MSG LOCK (SSML)
SET STRAP MSG CONTROL (SSMC)
SET STRAP MSG DATA (SSMD)
Configured Revision ID (CRID_UIP)
SLP S0 DEBUG REG0 (SLP_S0_DBG_0)
SLP S0 DEBUG REG1 (SLP_S0_DBG_1)
SLP S0 DEBUG REG2 (SLP_S0_DBG_2)
HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1)
HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2)
HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3)
HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)
HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)
HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6)
EXT FET RAMP CFG (EXT_FET_RAMP_CFG)
VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)
Always Running Timer Value 31:0 (ARTV_31_0)
Always Running Timer Value 63:32 (ARTV_63_32)
Timed GPIO Control 0 (TGPIOCTL0)
Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32)
Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0)
Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0)
Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32)
Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)
Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)
Timed GPIO Control 1 (TGPIOCTL1)
Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32)
Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0)
Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0)
Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32)
Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)
Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)
Min Temperature (MIN_TEMP)
Max Temperature (MAX_TEMP)
Catastrophic Trip Point Enable (CTEN)
EC Thermal Sensor Reporting Enable (ECRPTEN)
Throttle Level (TL)
Thermal Sensor Alert High Value (TSAHV)
Thermal Sensor Alert Low Value (TSALV)
Thermal Alert Trip Status (TAS)
Processor Hot Level Control (PHLC)
Temperature Sensor Control and Status (TSS0)
Low Power Mode Enable (LPM_EN)
Wake Alarm Device Timer: AC (WADT_AC)
Wake Alarm Device Timer: DC (WADT_DC)
Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)
Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)
Power and Reset Status (PRSTS)
Power Management Configuration Reg 1 (PM_CFG)
S3 Power Gating Policies (S3_PWRGATE_POL)
S4 Power Gating Policies (S4_PWRGATE_POL)
S5 Power Gating Policies (S5_PWRGATE_POL)
DeepSx Configuration (DSX_CFG)
Power Management Configuration Reg 2 (PM_CFG2)
Power Management Configuration Reg 3 (PM_CFG3)
CPU Early Power-on Configuration (CPU_EPOC)
ACPI Timer Control (ACPI_TMR_CTL)
Last TSC Alarm Value[31:0] (TSC_ALARM_LO)
Last TSC Alarm Value[63:32] (TSC_ALARM_HI)
GPIO Configuration (GPIO_CFG)
Host Partition Reset Causes (HPR_CAUSE0)
Latency Limit Residency 0 (LAT_LIM_RES_0)
Latency Limit Residency 1 (LAT_LIM_RES_1)
Latency Limit Residency 2 (LAT_LIM_RES_2)
SLP_S0 Residency (SLP_S0_RESIDENCY)
Latency Limit Control (LATENCY_LIMIT_CONTROL)
Chipset Initialization Register 1B1C (CPPMVRIC)
Chipset initialization 1B4C (CPPMVRIC2)
ACPI Control (ACTL)
S0 Residency (S0_RES)
PGD PG_ACK Status Register 0 (PPASR0)
PGD PG_ACK Status Register 1 (PPASR1)
PGD PFET Enable Ack Status Register 0 (PPFEAR0)
PGD PFET Enable Ack Status Register 1 (PPFEAR1)
PGD PG_REQ Status Register 0 (PPRSR0)
PGD PG_REQ Status Register 1 (PPRSR1)
PMC PCI Configuration
PMC PCI Configuration Device Vendor ID (DEVVENDID) STATUSCOMMAND Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) 32-bit Base Address Register (BAR) BAR HIGH (BAR_HIGH) 32-bit Base Address Register1 (BAR1) BAR1 HIGH (BAR1_HIGH) Bar 2 (BAR2) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR) CAPABILITY PTR (CAPABILITYPTR) INTERRUPT REG Interrupt Register (INTERRUPTREG) POWER CAP ID PowerManagement Capability ID (POWERCAPID) PME CTRL STATUS (PMECTRLSTATUS) PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD) DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) GEN REG RW1 (GEN_REGRW1) GEN REG RW2 (GEN_REGRW2) GEN REG RW3 (GEN_REGRW3) GEN REG RW4 (GEN_REGRW4) GEN INPUT REG (GEN_INPUT_REG)
Device Vendor ID (DEVVENDID)
STATUSCOMMAND Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Bar 2 (BAR2)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)
CAPABILITY PTR (CAPABILITYPTR)
INTERRUPT REG Interrupt Register (INTERRUPTREG)
POWER CAP ID PowerManagement Capability ID (POWERCAPID)
PME CTRL STATUS (PMECTRLSTATUS)
PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)
DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
GEN REG RW1 (GEN_REGRW1)
GEN REG RW2 (GEN_REGRW2)
GEN REG RW3 (GEN_REGRW3)
GEN REG RW4 (GEN_REGRW4)
GEN INPUT REG (GEN_INPUT_REG)
SSRAM PCI Configuration
SSRAM PCI Configuration Device Vendor ID (DEVVENDID) STATUSCOMMAND Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) 32-bit Base Address Register (BAR) BAR HIGH (BAR_HIGH) 32-bit Base Address Register1 (BAR1) BAR1 HIGH (BAR1_HIGH) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR) CAPABILITY PTR (CAPABILITYPTR) INTERRUPT REG Interrupt Register (INTERRUPTREG) POWER CAP ID PowerManagement Capability ID (POWERCAPID) PME CTRL STATUS (PMECTRLSTATUS) PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD) DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) GEN REG RW1 (GEN_REGRW1) GEN REG RW2 (GEN_REGRW2) GEN REG RW3 (GEN_REGRW3) GEN REG RW4 (GEN_REGRW4) GEN INPUT REG (GEN_INPUT_REG)
Device Vendor ID (DEVVENDID)
STATUSCOMMAND Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)
CAPABILITY PTR (CAPABILITYPTR)
INTERRUPT REG Interrupt Register (INTERRUPTREG)
POWER CAP ID PowerManagement Capability ID (POWERCAPID)
PME CTRL STATUS (PMECTRLSTATUS)
PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)
DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
GEN REG RW1 (GEN_REGRW1)
GEN REG RW2 (GEN_REGRW2)
GEN REG RW3 (GEN_REGRW3)
GEN REG RW4 (GEN_REGRW4)
GEN INPUT REG (GEN_INPUT_REG)
USB Type-C Subsystem-PCI Root Port Configuration (D7:F0/F1/F2/F3)
USB Type-C Subsystem-PCI Root Port Configuration (D7:F0/F1/F2/F3) Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information (INTR) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) FPB Capability Header (FPBCAP) FPB Capabilities Register (FPBCAPR) FPB RID Vector Control 1 (FPBRIDVC1) FPB RID Vector Control 2 (FPBRIDVC2) FPB MEM Low Vector Control (FPBMEMLVC) FPB MEM High Vector Control 1 (FPBMEMHVC1) FPB MEM High Vector Control 2 (FPBMEMHVC2) FPB Vector Access Control (FPBVAC) FPB Vector Access Data (FPBVD) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Header Log (HL_DW1) Header Log (HL_DW2) Header Log (HL_DW3) Header Log (HL_DW4) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS)
Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information (INTR)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
FPB Capability Header (FPBCAP)
FPB Capabilities Register (FPBCAPR)
FPB RID Vector Control 1 (FPBRIDVC1)
FPB RID Vector Control 2 (FPBRIDVC2)
FPB MEM Low Vector Control (FPBMEMLVC)
FPB MEM High Vector Control 1 (FPBMEMHVC1)
FPB MEM High Vector Control 2 (FPBMEMHVC2)
FPB Vector Access Control (FPBVAC)
FPB Vector Access Data (FPBVD)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Header Log (HL_DW1)
Header Log (HL_DW2)
Header Log (HL_DW3)
Header Log (HL_DW4)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Lane 0 And Lane 1 Equalization Control (L01EC)
Lane 2 And Lane 3 Equalization Control (L23EC)
Lane 4 And Lane 5 Equalization Control (L45EC)
Lane 6 And Lane 7 Equalization Control (L67EC)
Lane 8 And Lane 9 Equalization Control (L89EC)
Lane 10 And Lane 11 Equalization Control (L1011EC)
Lane 12 And Lane 13 Equalization Control (L1213EC)
Lane 14 And Lane 15 Equalization Control (L1415EC)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
USB xHCI MMIO
USB xHCI MMIO Capability Registers Length (CAPLENGTH) Host Controller Interface Version Number (HCIVERSION) Structural Parameters 1 (HCSPARAMS1) Structural Parameters 2 (HCSPARAMS2) Structural Parameters 3 (HCSPARAMS3) Capability Parameters (HCCPARAMS) Doorbell Offset (DBOFF) Runtime Register Space Offset (RTSOFF) USB Command (USBCMD) USB Status (USBSTS) Page Size (PAGESIZE) Device Notification Control (DNCTRL) Command Ring Low (CRCR_LO) Command Ring High (CRCR_HI) Device Context Base Address Array Pointer Low (DCBAAP_LO) Device Context Base Address Array Pointer High (DCBAAP_HI) Configure Reg (CONFIG) Port Status AndControl USB2 (PORTSC1) Port Power Management Status Aand Control USB2 (PORTPMSC1) Port X Hardware LPM Control Register (PORTHLPMC1) Port Status And Control USB3 (PORTSC2) Port Power Management Status And Control USB3 (PORTPMSC2) USB3 Port Link Info (PORTLI2) Port Status And Control USB3 (PORTSC3) Port Power Management Status And Control USB3 (PORTPMSC3) USB3 Port Link Info (PORTLI3) Port Status And Control USB3 (PORTSC4) Port Power Management Status And Control USB3 (PORTPMSC4) USB3 Port Link Info (PORTLI4) Port Status And Control USB3 (PORTSC5) Port Power Management Status And Control USB3 (PORTPMSC5) USB3 Port Link Info (PORTLI5) Microframe Index (RTMFINDEX) Interrupter Management (IMAN0) Interrupter Moderation (IMOD0) Event Ring Segment Table Size (ERSTSZ0) Event Ring Segment Table Base Address Low (ERSTBA_LO0) Event Ring Segment Table Base Address High (ERSTBA_HI0) Event Ring Dequeue Pointer Low (ERDP_LO0) Event Ring Dequeue Pointer High (ERDP_HI0) Interrupter Management (IMAN1) Interrupter Moderation (IMOD1) Event Ring Segment Table Size (ERSTSZ1) Event Ring Segment Table Base Address Low (ERSTBA_LO1) Event Ring Segment Table Base Address High (ERSTBA_HI1) Event Ring Dequeue Pointer Low (ERDP_LO1) Event Ring Dequeue Pointer High (ERDP_HI1) Interrupter Management (IMAN2) Interrupter Moderation (IMOD2) Event Ring Segment Table Size (ERSTSZ2) Event Ring Segment Table Base Address Low (ERSTBA_LO2) Event Ring Segment Table Base Address High (ERSTBA_HI2) Event Ring Dequeue Pointer Low (ERDP_LO2) Event Ring Dequeue Pointer High (ERDP_HI2) Interrupter Management (IMAN3) Interrupter Moderation (IMOD3) Event Ring Segment Table Size (ERSTSZ3) Event Ring Segment Table Base Address Low (ERSTBA_LO3) Event Ring Segment Table Base Address High (ERSTBA_HI3) Event Ring Dequeue Pointer Low (ERDP_LO3) Event Ring Dequeue Pointer High (ERDP_HI3) Interrupter Management (IMAN4) Interrupter Moderation (IMOD4) Event Ring Segment Table Size (ERSTSZ4) Event Ring Segment Table Base Address Low (ERSTBA_LO4) Event Ring Segment Table Base Address High (ERSTBA_HI4) Event Ring Dequeue Pointer Low (ERDP_LO4) Event Ring Dequeue Pointer High (ERDP_HI4) Interrupter Management (IMAN5) Interrupter Moderation (IMOD5) Event Ring Segment Table Size (ERSTSZ5) Event Ring Segment Table Base Address Low (ERSTBA_LO5) Event Ring Segment Table Base Address High (ERSTBA_HI5) Event Ring Dequeue Pointer Low (ERDP_LO5) Event Ring Dequeue Pointer High (ERDP_HI5) Interrupter Management (IMAN6) Interrupter Moderation (IMOD6) Event Ring Segment Table Size (ERSTSZ6) Event Ring Segment Table Base Address Low (ERSTBA_LO6) Event Ring Segment Table Base Address High (ERSTBA_HI6) Event Ring Dequeue Pointer Low (ERDP_LO6) Event Ring Dequeue Pointer High (ERDP_HI6) Interrupter Management (IMAN7) Interrupter Moderation (IMOD7) Event Ring Segment Table Size (ERSTSZ7) Event Ring Segment Table Base Address Low (ERSTBA_LO7) Event Ring Segment Table Base Address High (ERSTBA_HI7) Event Ring Dequeue Pointer Low (ERDP_LO7) Event Ring Dequeue Pointer High (ERDP_HI7) Door Bell (DB0) Door Bell (DB1) Door Bell (DB2) Door Bell (DB3) Door Bell (DB4) Door Bell (DB5) Door Bell (DB6) Door Bell (DB7) Door Bell (DB8) Door Bell (DB9) Door Bell (DB10) Door Bell (DB11) Door Bell (DB12) Door Bell (DB13) Door Bell (DB14) Door Bell (DB15) Door Bell (DB16) Door Bell (DB17) Door Bell (DB18) Door Bell (DB19) Door Bell (DB20) Door Bell (DB21) Door Bell (DB22) Door Bell (DB23) Door Bell (DB24) Door Bell (DB25) Door Bell (DB26) Door Bell (DB27) Door Bell (DB28) Door Bell (DB29) Door Bell (DB30) Door Bell (DB31) Door Bell (DB32) XECP SUPP USB2_1 (XECP_SUPP_USB2_1) XECP SUPP USB3_3 (XECP_SUPP_USB2_3) XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4) XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5) XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6) XECP SUPP USB3_0 (XECP_SUPP_USB3_0) XECP SUPP USB3_1 (XECP_SUPP_USB3_1) XECP SUPP USB3_2 (XECP_SUPP_USB3_2) XECP SUPP USB3_3 (XECP_SUPP_USB3_3) XECP SUPP USB3_4 (XECP_SUPP_USB3_4) XECP SUPP USB3_5 (XECP_SUPP_USB3_5) XECP SUPP USB3_6 (XECP_SUPP_USB3_6) XECP SUPP USB3_7 (XECP_SUPP_USB3_7) Host Control Scheduler (HOST_CTRL_SCH_REG) Power Management Control (PMCTRL_REG) Host Controller Misc Reg (HOST_CTRL_MISC_REG) Super Speed Port Enable (SSPE_REG) AUX Power Management Control (AUX_CTRL_REG1) SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2) USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3) USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4) Power Scheduler Control-0 (PWR_SCHED_CTRL0) Power Scheduler Control-1 (PWR_SCHED_CTRL2) AUX Power Management Control (AUX_CTRL_REG2) USB2 PHY Power Management Control (USB2_PHY_PMC) XHCI Aux Clock Control Register (XHCI_AUX_CCR) XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) XHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2) XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC) XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC) XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC) LFPS On Count (LFPSONCOUNT_REG) USB2 Power Management Control (USB2PMCTRL_REG) USB Legacy Support Capability (USBLEGSUP) USB Legacy Support Control Status (USBLEGCTLSTS) Port Disable Override Capability Register (PDO_CAPABILITY) Command Reg (CMD_MMIO) Device Status (STS_MMIO) Revision ID (RID_MMIO) Programming Interface (PI_MMIO) Sub Class Code (SCC_MMIO) Base Class Code (BCC_MMIO) Cache Line Size (CLS_MMIO) Master Latency Timer (MLT_MMIO) Header Type (HT_MMIO) Memory Base Address (MBAR_MMIO) USB Subsystem Vendor ID (SSVID_MMIO) USB Subsystem ID (SSID_MMIO) Capabilities Pointer (CAP_PTR_MMIO) Interrupt Line (ILINE_MMIO) Interrupt Pin (IPIN_MMIO) Serial Bus Release Number (SBRN_MMIO) Frame Length Adjustment (FLADJ_MMIO) Best Effort Service Latency (BESL_MMIO) PCI Power Management Capability ID (PM_CID_MMIO) Next Item Pointer 1 (PM_NEXT_MMIO) Power Management Capabilities (PM_CAP_MMIO) Power Management Control/Status (PM_CS_MMIO) Message Signaled Interrupt CID (MSI_CID_MMIO) Next Item Pointer (MSI_NEXT_MMIO) Message Signaled Interrupt Message Control (MSI_MCTL_MMIO) Message Signaled Interrupt Message Address (MSI_MAD_MMIO) Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO) Message Signaled Interrupt Message Data (MSI_MD_MMIO) High Speed Configuration 2 (HSCFG2_MMIO) GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG) GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG) MICROFRAME TIME REG (MICROFRAME_TIME_REG) Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG) GLOBAL TIME HI REG (GLOBAL_TIME_HI_REG) Dublin HOST_CTRL_USB3_LOCAL_LPBK_RPTR (HOST_CTRL_USB3_LOCAL_LPBK_RPTR) Host Ctrl Usb3 Master Loopback Register (HOST_CTRL_USB3_MSTR_LPBK) Host Ctrl Usb3 Blr Comp Register (HOST_CTRL_USB3_BLR_COMP) Host Ctrl Ssp Dis Register (HOST_CTRL_SSP_DIS) XHCI USB2 Overcurrent Pin Mapping (U2OCM1) XHCI USB2 Overcurrent Pin Mapping (U2OCM2) XHCI USB2 Overcurrent Pin Mapping (U2OCM3) XHCI USB2 Overcurrent Pin Mapping (U2OCM4) XHCI USB3 Overcurrent Pin Mapping (U3OCM1) XHCI USB3 Overcurrent Pin Mapping (U3OCM2) XHCI USB3 Overcurrent Pin Mapping (U3OCM3) XHCI USB3 Overcurrent Pin Mapping (U3OCM4)
Capability Registers Length (CAPLENGTH)
Host Controller Interface Version Number (HCIVERSION)
Structural Parameters 1 (HCSPARAMS1)
Structural Parameters 2 (HCSPARAMS2)
Structural Parameters 3 (HCSPARAMS3)
Capability Parameters (HCCPARAMS)
Doorbell Offset (DBOFF)
Runtime Register Space Offset (RTSOFF)
USB Command (USBCMD)
USB Status (USBSTS)
Page Size (PAGESIZE)
Device Notification Control (DNCTRL)
Command Ring Low (CRCR_LO)
Command Ring High (CRCR_HI)
Device Context Base Address Array Pointer Low (DCBAAP_LO)
Device Context Base Address Array Pointer High (DCBAAP_HI)
Configure Reg (CONFIG)
Port Status AndControl USB2 (PORTSC1)
Port Power Management Status Aand Control USB2 (PORTPMSC1)
Port X Hardware LPM Control Register (PORTHLPMC1)
Port Status And Control USB3 (PORTSC2)
Port Power Management Status And Control USB3 (PORTPMSC2)
USB3 Port Link Info (PORTLI2)
Port Status And Control USB3 (PORTSC3)
Port Power Management Status And Control USB3 (PORTPMSC3)
USB3 Port Link Info (PORTLI3)
Port Status And Control USB3 (PORTSC4)
Port Power Management Status And Control USB3 (PORTPMSC4)
USB3 Port Link Info (PORTLI4)
Port Status And Control USB3 (PORTSC5)
Port Power Management Status And Control USB3 (PORTPMSC5)
USB3 Port Link Info (PORTLI5)
Microframe Index (RTMFINDEX)
Interrupter Management (IMAN0)
Interrupter Moderation (IMOD0)
Event Ring Segment Table Size (ERSTSZ0)
Event Ring Segment Table Base Address Low (ERSTBA_LO0)
Event Ring Segment Table Base Address High (ERSTBA_HI0)
Event Ring Dequeue Pointer Low (ERDP_LO0)
Event Ring Dequeue Pointer High (ERDP_HI0)
Interrupter Management (IMAN1)
Interrupter Moderation (IMOD1)
Event Ring Segment Table Size (ERSTSZ1)
Event Ring Segment Table Base Address Low (ERSTBA_LO1)
Event Ring Segment Table Base Address High (ERSTBA_HI1)
Event Ring Dequeue Pointer Low (ERDP_LO1)
Event Ring Dequeue Pointer High (ERDP_HI1)
Interrupter Management (IMAN2)
Interrupter Moderation (IMOD2)
Event Ring Segment Table Size (ERSTSZ2)
Event Ring Segment Table Base Address Low (ERSTBA_LO2)
Event Ring Segment Table Base Address High (ERSTBA_HI2)
Event Ring Dequeue Pointer Low (ERDP_LO2)
Event Ring Dequeue Pointer High (ERDP_HI2)
Interrupter Management (IMAN3)
Interrupter Moderation (IMOD3)
Event Ring Segment Table Size (ERSTSZ3)
Event Ring Segment Table Base Address Low (ERSTBA_LO3)
Event Ring Segment Table Base Address High (ERSTBA_HI3)
Event Ring Dequeue Pointer Low (ERDP_LO3)
Event Ring Dequeue Pointer High (ERDP_HI3)
Interrupter Management (IMAN4)
Interrupter Moderation (IMOD4)
Event Ring Segment Table Size (ERSTSZ4)
Event Ring Segment Table Base Address Low (ERSTBA_LO4)
Event Ring Segment Table Base Address High (ERSTBA_HI4)
Event Ring Dequeue Pointer Low (ERDP_LO4)
Event Ring Dequeue Pointer High (ERDP_HI4)
Interrupter Management (IMAN5)
Interrupter Moderation (IMOD5)
Event Ring Segment Table Size (ERSTSZ5)
Event Ring Segment Table Base Address Low (ERSTBA_LO5)
Event Ring Segment Table Base Address High (ERSTBA_HI5)
Event Ring Dequeue Pointer Low (ERDP_LO5)
Event Ring Dequeue Pointer High (ERDP_HI5)
Interrupter Management (IMAN6)
Interrupter Moderation (IMOD6)
Event Ring Segment Table Size (ERSTSZ6)
Event Ring Segment Table Base Address Low (ERSTBA_LO6)
Event Ring Segment Table Base Address High (ERSTBA_HI6)
Event Ring Dequeue Pointer Low (ERDP_LO6)
Event Ring Dequeue Pointer High (ERDP_HI6)
Interrupter Management (IMAN7)
Interrupter Moderation (IMOD7)
Event Ring Segment Table Size (ERSTSZ7)
Event Ring Segment Table Base Address Low (ERSTBA_LO7)
Event Ring Segment Table Base Address High (ERSTBA_HI7)
Event Ring Dequeue Pointer Low (ERDP_LO7)
Event Ring Dequeue Pointer High (ERDP_HI7)
Door Bell (DB0)
Door Bell (DB1)
Door Bell (DB2)
Door Bell (DB3)
Door Bell (DB4)
Door Bell (DB5)
Door Bell (DB6)
Door Bell (DB7)
Door Bell (DB8)
Door Bell (DB9)
Door Bell (DB10)
Door Bell (DB11)
Door Bell (DB12)
Door Bell (DB13)
Door Bell (DB14)
Door Bell (DB15)
Door Bell (DB16)
Door Bell (DB17)
Door Bell (DB18)
Door Bell (DB19)
Door Bell (DB20)
Door Bell (DB21)
Door Bell (DB22)
Door Bell (DB23)
Door Bell (DB24)
Door Bell (DB25)
Door Bell (DB26)
Door Bell (DB27)
Door Bell (DB28)
Door Bell (DB29)
Door Bell (DB30)
Door Bell (DB31)
Door Bell (DB32)
XECP SUPP USB2_1 (XECP_SUPP_USB2_1)
XECP SUPP USB3_3 (XECP_SUPP_USB2_3)
XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4)
XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5)
XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6)
XECP SUPP USB3_0 (XECP_SUPP_USB3_0)
XECP SUPP USB3_1 (XECP_SUPP_USB3_1)
XECP SUPP USB3_2 (XECP_SUPP_USB3_2)
XECP SUPP USB3_3 (XECP_SUPP_USB3_3)
XECP SUPP USB3_4 (XECP_SUPP_USB3_4)
XECP SUPP USB3_5 (XECP_SUPP_USB3_5)
XECP SUPP USB3_6 (XECP_SUPP_USB3_6)
XECP SUPP USB3_7 (XECP_SUPP_USB3_7)
Host Control Scheduler (HOST_CTRL_SCH_REG)
Power Management Control (PMCTRL_REG)
Host Controller Misc Reg (HOST_CTRL_MISC_REG)
Super Speed Port Enable (SSPE_REG)
AUX Power Management Control (AUX_CTRL_REG1)
SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)
USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)
USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)
USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)
USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)
Power Scheduler Control-0 (PWR_SCHED_CTRL0)
Power Scheduler Control-1 (PWR_SCHED_CTRL2)
AUX Power Management Control (AUX_CTRL_REG2)
USB2 PHY Power Management Control (USB2_PHY_PMC)
XHCI Aux Clock Control Register (XHCI_AUX_CCR)
XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1)
XHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)
XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC)
XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC)
XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)
LFPS On Count (LFPSONCOUNT_REG)
USB2 Power Management Control (USB2PMCTRL_REG)
USB Legacy Support Capability (USBLEGSUP)
USB Legacy Support Control Status (USBLEGCTLSTS)
Port Disable Override Capability Register (PDO_CAPABILITY)
Command Reg (CMD_MMIO)
Device Status (STS_MMIO)
Revision ID (RID_MMIO)
Programming Interface (PI_MMIO)
Sub Class Code (SCC_MMIO)
Base Class Code (BCC_MMIO)
Cache Line Size (CLS_MMIO)
Master Latency Timer (MLT_MMIO)
Header Type (HT_MMIO)
Memory Base Address (MBAR_MMIO)
USB Subsystem Vendor ID (SSVID_MMIO)
USB Subsystem ID (SSID_MMIO)
Capabilities Pointer (CAP_PTR_MMIO)
Interrupt Line (ILINE_MMIO)
Interrupt Pin (IPIN_MMIO)
Serial Bus Release Number (SBRN_MMIO)
Frame Length Adjustment (FLADJ_MMIO)
Best Effort Service Latency (BESL_MMIO)
PCI Power Management Capability ID (PM_CID_MMIO)
Next Item Pointer 1 (PM_NEXT_MMIO)
Power Management Capabilities (PM_CAP_MMIO)
Power Management Control/Status (PM_CS_MMIO)
Message Signaled Interrupt CID (MSI_CID_MMIO)
Next Item Pointer (MSI_NEXT_MMIO)
Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)
Message Signaled Interrupt Message Address (MSI_MAD_MMIO)
Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)
Message Signaled Interrupt Message Data (MSI_MD_MMIO)
High Speed Configuration 2 (HSCFG2_MMIO)
GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)
GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG)
MICROFRAME TIME REG (MICROFRAME_TIME_REG)
Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG)
GLOBAL TIME HI REG (GLOBAL_TIME_HI_REG)
Dublin HOST_CTRL_USB3_LOCAL_LPBK_RPTR (HOST_CTRL_USB3_LOCAL_LPBK_RPTR)
Host Ctrl Usb3 Master Loopback Register (HOST_CTRL_USB3_MSTR_LPBK)
Host Ctrl Usb3 Blr Comp Register (HOST_CTRL_USB3_BLR_COMP)
Host Ctrl Ssp Dis Register (HOST_CTRL_SSP_DIS)
XHCI USB2 Overcurrent Pin Mapping (U2OCM1)
XHCI USB2 Overcurrent Pin Mapping (U2OCM2)
XHCI USB2 Overcurrent Pin Mapping (U2OCM3)
XHCI USB2 Overcurrent Pin Mapping (U2OCM4)
XHCI USB3 Overcurrent Pin Mapping (U3OCM1)
XHCI USB3 Overcurrent Pin Mapping (U3OCM2)
XHCI USB3 Overcurrent Pin Mapping (U3OCM3)
USB xHCI PCI Configuration
USB xHCI PCI Configuration Vendor ID (VID) Device ID (DID) Command Reg (CMD) Device Status (STS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Master Latency Timer (MLT) Header Type (HT) Memory Base Address (MBAR) USB Subsystem Vendor ID (SSVID) USB Subsystem ID (SSID) Capabilities Pointer (CAP_PTR) Interrupt Line (ILINE) Interrupt Pin (IPIN) XHC System Bus Configuration 1 (XHCC1) XHC System Bus Configuration 2 (XHCC2) Clock Gating (XHCLKGTEN) Audio Time Synchronization (AUDSYNC) Serial Bus Release Number (SBRN) Frame Length Adjustment (FLADJ) Best Effort Service Latency (BESL) PCI Power Management Capability ID (PM_CID) Next Item Pointer 1 (PM_NEXT) Power Management Capabilities (PM_CAP) Power Management Control/Status (PM_CS) Message Signaled Interrupt CID (MSI_CID) Next Item Pointer (MSI_NEXT) Message Signaled Interrupt Message Control (MSI_MCTL) Message Signaled Interrupt Message Address (MSI_MAD) Message Signaled Interrupt Upper Address (MSI_MUAD) Message Signaled Interrupt Message Data (MSI_MD)
Vendor ID (VID)
Device ID (DID)
Command Reg (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HT)
Memory Base Address (MBAR)
USB Subsystem Vendor ID (SSVID)
USB Subsystem ID (SSID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (ILINE)
Interrupt Pin (IPIN)
XHC System Bus Configuration 1 (XHCC1)
XHC System Bus Configuration 2 (XHCC2)
Clock Gating (XHCLKGTEN)
Audio Time Synchronization (AUDSYNC)
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Best Effort Service Latency (BESL)
PCI Power Management Capability ID (PM_CID)
Next Item Pointer 1 (PM_NEXT)
Power Management Capabilities (PM_CAP)
Power Management Control/Status (PM_CS)
Message Signaled Interrupt CID (MSI_CID)
Next Item Pointer (MSI_NEXT)
Message Signaled Interrupt Message Control (MSI_MCTL)
Message Signaled Interrupt Message Address (MSI_MAD)
Message Signaled Interrupt Upper Address (MSI_MUAD)
Message Signaled Interrupt Message Data (MSI_MD)

USB xHCI MMIO Registers

Summary of Bus: (), Device: (), Function: (), Type: (MEM)

Offset

Size (Bytes)

Register Name (Register Symbol)

Scope

Default Value

0h

1

Capability Registers Length (CAPLENGTH)

Package

80h

2h

2

Host Controller Interface Version Number (HCIVERSION)

Package

0120h

4h

4

Structural Parameters 1 (HCSPARAMS1)

Package

05000840h

8h

4

Structural Parameters 2 (HCSPARAMS2)

Package

14200054h

ch

4

Structural Parameters 3 (HCSPARAMS3)

Package

00A0000Ah

10h

4

Capability Parameters (HCCPARAMS)

Package

20007FC1h

14h

4

Doorbell Offset (DBOFF)

Package

00003000h

18h

4

Runtime Register Space Offset (RTSOFF)

Package

00002000h

80h

4

USB Command (USBCMD)

Package

00000000h

84h

4

USB Status (USBSTS)

Package

00000001h

88h

4

Page Size (PAGESIZE)

Package

00000001h

94h

4

Device Notification Control (DNCTRL)

Package

00000000h

98h

4

Command Ring Low (CRCR_​LO)

Package

00000000h

9ch

4

Command Ring High (CRCR_​HI)

Package

00000000h

b0h

4

Device Context Base Address Array Pointer Low (DCBAAP_​LO)

Package

00000000h

b4h

4

Device Context Base Address Array Pointer High (DCBAAP_​HI)

Package

00000000h

b8h

4

Configure Reg (CONFIG)

Package

00000000h

480h

4

Port Status AndControl USB2 (PORTSC1)

Package

000002A0h

484h

4

Port Power Management Status Aand Control USB2 (PORTPMSC1)

Package

00000000h

48ch

4

Port X Hardware LPM Control Register (PORTHLPMC1)

Package

00000000h

490h

4

Port Status And Control USB3 (PORTSC2)

Package

00000000h

494h

4

Port Power Management Status And Control USB3 (PORTPMSC2)

Package

00000000h

498h

4

USB3 Port Link Info (PORTLI2)

Package

00000000h

4a0h

4

Port Status And Control USB3 (PORTSC3)

Package

00000000h

4a4h

4

Port Power Management Status And Control USB3 (PORTPMSC3)

Package

00000000h

4a8h

4

USB3 Port Link Info (PORTLI3)

Package

00000000h

4b0h

4

Port Status And Control USB3 (PORTSC4)

Package

00000000h

4b4h

4

Port Power Management Status And Control USB3 (PORTPMSC4)

Package

00000000h

4b8h

4

USB3 Port Link Info (PORTLI4)

Package

00000000h

4c0h

4

Port Status And Control USB3 (PORTSC5)

Package

00000000h

4c4h

4

Port Power Management Status And Control USB3 (PORTPMSC5)

Package

00000000h

4c8h

4

USB3 Port Link Info (PORTLI5)

Package

00000000h

2000h

4

Microframe Index (RTMFINDEX)

Package

00000000h

2020h

4

Interrupter Management (IMAN0)

Package

00000000h

2024h

4

Interrupter Moderation (IMOD0)

Package

00000FA0h

2028h

4

Event Ring Segment Table Size (ERSTSZ0)

Package

00000000h

2030h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO0)

Package

00000000h

2034h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI0)

Package

00000000h

2038h

4

Event Ring Dequeue Pointer Low (ERDP_​LO0)

Package

00000000h

203ch

4

Event Ring Dequeue Pointer High (ERDP_​HI0)

Package

00000000h

2040h

4

Interrupter Management (IMAN1)

Package

00000000h

2044h

4

Interrupter Moderation (IMOD1)

Package

00000000h

2048h

4

Event Ring Segment Table Size (ERSTSZ1)

Package

00000000h

2050h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO1)

Package

00000000h

2054h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI1)

Package

00000000h

2058h

4

Event Ring Dequeue Pointer Low (ERDP_​LO1)

Package

00000000h

205ch

4

Event Ring Dequeue Pointer High (ERDP_​HI1)

Package

00000000h

2060h

4

Interrupter Management (IMAN2)

Package

00000000h

2064h

4

Interrupter Moderation (IMOD2)

Package

00000FA0h

2068h

4

Event Ring Segment Table Size (ERSTSZ2)

Package

00000000h

2070h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO2)

Package

00000000h

2074h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI2)

Package

00000000h

2078h

4

Event Ring Dequeue Pointer Low (ERDP_​LO2)

Package

00000000h

207ch

4

Event Ring Dequeue Pointer High (ERDP_​HI2)

Package

00000000h

2080h

4

Interrupter Management (IMAN3)

Package

00000000h

2084h

4

Interrupter Moderation (IMOD3)

Package

00000000h

2088h

4

Event Ring Segment Table Size (ERSTSZ3)

Package

00000000h

2090h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO3)

Package

00000000h

2094h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI3)

Package

00000000h

2098h

4

Event Ring Dequeue Pointer Low (ERDP_​LO3)

Package

00000000h

209ch

4

Event Ring Dequeue Pointer High (ERDP_​HI3)

Package

00000000h

20a0h

4

Interrupter Management (IMAN4)

Package

00000000h

20a4h

4

Interrupter Moderation (IMOD4)

Package

00000000h

20a8h

4

Event Ring Segment Table Size (ERSTSZ4)

Package

00000000h

20b0h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO4)

Package

00000000h

20b4h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI4)

Package

00000000h

20b8h

4

Event Ring Dequeue Pointer Low (ERDP_​LO4)

Package

00000000h

20bch

4

Event Ring Dequeue Pointer High (ERDP_​HI4)

Package

00000000h

20c0h

4

Interrupter Management (IMAN5)

Package

00000000h

20c4h

4

Interrupter Moderation (IMOD5)

Package

00000000h

20c8h

4

Event Ring Segment Table Size (ERSTSZ5)

Package

00000000h

20d0h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO5)

Package

00000000h

20d4h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI5)

Package

00000000h

20d8h

4

Event Ring Dequeue Pointer Low (ERDP_​LO5)

Package

00000000h

20dch

4

Event Ring Dequeue Pointer High (ERDP_​HI5)

Package

00000000h

20e0h

4

Interrupter Management (IMAN6)

Package

00000000h

20e4h

4

Interrupter Moderation (IMOD6)

Package

00000000h

20e8h

4

Event Ring Segment Table Size (ERSTSZ6)

Package

00000000h

20f0h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO6)

Package

00000000h

20f4h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI6)

Package

00000000h

20f8h

4

Event Ring Dequeue Pointer Low (ERDP_​LO6)

Package

00000000h

20fch

4

Event Ring Dequeue Pointer High (ERDP_​HI6)

Package

00000000h

2100h

4

Interrupter Management (IMAN7)

Package

00000000h

2104h

4

Interrupter Moderation (IMOD7)

Package

00000000h

2108h

4

Event Ring Segment Table Size (ERSTSZ7)

Package

00000000h

2110h

4

Event Ring Segment Table Base Address Low (ERSTBA_​LO7)

Package

00000000h

2114h

4

Event Ring Segment Table Base Address High (ERSTBA_​HI7)

Package

00000000h

2118h

4

Event Ring Dequeue Pointer Low (ERDP_​LO7)

Package

00000000h

211ch

4

Event Ring Dequeue Pointer High (ERDP_​HI7)

Package

00000000h

3000h

4

Door Bell (DB0)

Package

00000000h

3004h

4

Door Bell (DB1)

Package

00000000h

3008h

4

Door Bell (DB2)

Package

00000000h

300ch

4

Door Bell (DB3)

Package

00000000h

3010h

4

Door Bell (DB4)

Package

00000000h

3014h

4

Door Bell (DB5)

Package

00000000h

3018h

4

Door Bell (DB6)

Package

00000000h

301ch

4

Door Bell (DB7)

Package

00000000h

3020h

4

Door Bell (DB8)

Package

00000000h

3024h

4

Door Bell (DB9)

Package

00000000h

3028h

4

Door Bell (DB10)

Package

00000000h

302ch

4

Door Bell (DB11)

Package

00000000h

3030h

4

Door Bell (DB12)

Package

00000000h

3034h

4

Door Bell (DB13)

Package

00000000h

3038h

4

Door Bell (DB14)

Package

00000000h

303ch

4

Door Bell (DB15)

Package

00000000h

3040h

4

Door Bell (DB16)

Package

00000000h

3044h

4

Door Bell (DB17)

Package

00000000h

3048h

4

Door Bell (DB18)

Package

00000000h

304ch

4

Door Bell (DB19)

Package

00000000h

3050h

4

Door Bell (DB20)

Package

00000000h

3054h

4

Door Bell (DB21)

Package

00000000h

3058h

4

Door Bell (DB22)

Package

00000000h

305ch

4

Door Bell (DB23)

Package

00000000h

3060h

4

Door Bell (DB24)

Package

00000000h

3064h

4

Door Bell (DB25)

Package

00000000h

3068h

4

Door Bell (DB26)

Package

00000000h

306ch

4

Door Bell (DB27)

Package

00000000h

3070h

4

Door Bell (DB28)

Package

00000000h

3074h

4

Door Bell (DB29)

Package

00000000h

3078h

4

Door Bell (DB30)

Package

00000000h

307ch

4

Door Bell (DB31)

Package

00000000h

3080h

4

Door Bell (DB32)

Package

00000000h

8004h

4

XECP SUPP USB2_​1 (XECP_​SUPP_​USB2_​1)

Package

20425355h

800ch

4

XECP SUPP USB3_​3 (XECP_​SUPP_​USB2_​3)

Package

00000000h

8010h

4

XECP SUPP USB2_​4 Full Speed (XECP_​SUPP_​USB2_​4)

Package

000C0021h

8014h

4

XECP_​SUPP USB2_​5 Low Speed (XECP_​SUPP_​USB2_​5)

Package

05DC0012h

8018h

4

XECP SUPP USB2_​6 High Speed (XECP_​SUPP_​USB2_​6)

Package

01E00023h

8020h

4

XECP SUPP USB3_​0 (XECP_​SUPP_​USB3_​0)

Package

03201402h

8024h

4

XECP SUPP USB3_​1 (XECP_​SUPP_​USB3_​1)

Package

00000000h

8028h

4

XECP SUPP USB3_​2 (XECP_​SUPP_​USB3_​2)

Package

40000402h

802ch

4

XECP SUPP USB3_​3 (XECP_​SUPP_​USB3_​3)

Package

00000000h

8030h

4

XECP SUPP USB3_​4 (XECP_​SUPP_​USB3_​4)

Package

00050134h

8034h

4

XECP SUPP USB3_​5 (XECP_​SUPP_​USB3_​5)

Package

000A4135h

8038h

4

XECP SUPP USB3_​6 (XECP_​SUPP_​USB3_​6)

Package

000A4136h

803ch

4

XECP SUPP USB3_​7 (XECP_​SUPP_​USB3_​7)

Package

00144137h

8094h

4

Host Control Scheduler (HOST_​CTRL_​SCH_​REG)

Package

00C0E140h

80a4h

4

Power Management Control (PMCTRL_​REG)

Package

49ED509Ch

80b0h

4

Host Controller Misc Reg (HOST_​CTRL_​MISC_​REG)

Package

0080037Fh

80b8h

4

Super Speed Port Enable (SSPE_​REG)

Package

C0000000h

80e0h

4

AUX Power Management Control (AUX_​CTRL_​REG1)

Package

800018E0h

80ech

4

SuperSpeed Port Link Control (HOST_​CTRL_​PORT_​LINK_​REG)

Package

00000000h

80f0h

4

USB2 Port Link Control 1 (USB2_​LINK_​MGR_​CTRL_​REG1)

Package

000003A0h

80f4h

4

USB2 Port Link Control 2 (USB2_​LINK_​MGR_​CTRL_​REG2)

Package

80C40620h

80f8h

4

USB2 Port Link Control 3 (USB2_​LINK_​MGR_​CTRL_​REG3)

Package

F865EB6Bh

80fch

4

USB2 Port Link Control 4 (USB2_​LINK_​MGR_​CTRL_​REG4)

Package

02008003h

8140h

4

Power Scheduler Control-0 (PWR_​SCHED_​CTRL0)

Package

FF01903Ch

8144h

4

Power Scheduler Control-1 (PWR_​SCHED_​CTRL2)

Package

00000000h

8154h

4

AUX Power Management Control (AUX_​CTRL_​REG2)

Package

81190206h

8164h

4

USB2 PHY Power Management Control (USB2_​PHY_​PMC)

Package

000000FCh

816ch

4

XHCI Aux Clock Control Register (XHCI_​AUX_​CCR)

Package

003D003Ch

8174h

4

XHC Latency Tolerance Parameters LTV Control (XLTP_​LTV1)

Package

01400C01h

8178h

4

XHC Latency Tolerance Parameters LTV Control 2 (XLTP_​LTV2)

Package

000097FFh

817ch

4

XHC Latency Tolerance Parameters High Idle Time Control (XLTP_​HITC)

Package

00050002h

8180h

4

XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_​MITC)

Package

00050002h

8184h

4

XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_​LITC)

Package

00050002h

81b8h

4

LFPS On Count (LFPSONCOUNT_​REG)

Package

000420C8h

81c4h

4

USB2 Power Management Control (USB2PMCTRL_​REG)

Package

00822908h

846ch

4

USB Legacy Support Capability (USBLEGSUP)

Package

00002201h

8470h

4

USB Legacy Support Control Status (USBLEGCTLSTS)

Package

00000000h

84f4h

4

Port Disable Override Capability Register (PDO_​CAPABILITY)

Package

000003C6h

8604h

2

Command Reg (CMD_​MMIO)

Package

0000h

8606h

2

Device Status (STS_​MMIO)

Package

0290h

8608h

1

Revision ID (RID_​MMIO)

Package

XXh

8609h

1

Programming Interface (PI_​MMIO)

Package

30h

860ah

1

Sub Class Code (SCC_​MMIO)

Package

00h

860bh

1

Base Class Code (BCC_​MMIO)

Package

0Ch

860ch

1

Cache Line Size (CLS_​MMIO)

Package

00h

860dh

1

Master Latency Timer (MLT_​MMIO)

Package

00h

860eh

1

Header Type (HT_​MMIO)

Package

80h

8610h

8

Memory Base Address (MBAR_​MMIO)

Package

0000000000000004h

862ch

2

USB Subsystem Vendor ID (SSVID_​MMIO)

Package

0000h

862eh

2

USB Subsystem ID (SSID_​MMIO)

Package

0000h

8634h

1

Capabilities Pointer (CAP_​PTR_​MMIO)

Package

70h

863ch

1

Interrupt Line (ILINE_​MMIO)

Package

00h

863dh

1

Interrupt Pin (IPIN_​MMIO)

Package

00h

8660h

1

Serial Bus Release Number (SBRN_​MMIO)

Package

32h

8661h

1

Frame Length Adjustment (FLADJ_​MMIO)

Package

60h

8662h

1

Best Effort Service Latency (BESL_​MMIO)

Package

00h

8670h

1

PCI Power Management Capability ID (PM_​CID_​MMIO)

Package

01h

8671h

1

Next Item Pointer 1 (PM_​NEXT_​MMIO)

Package

80h

8672h

2

Power Management Capabilities (PM_​CAP_​MMIO)

Package

C1C3h

8674h

2

Power Management Control/Status (PM_​CS_​MMIO)

Package

0008h

8680h

1

Message Signaled Interrupt CID (MSI_​CID_​MMIO)

Package

05h

8681h

1

Next Item Pointer (MSI_​NEXT_​MMIO)

Package

90h

8682h

2

Message Signaled Interrupt Message Control (MSI_​MCTL_​MMIO)

Package

0086h

8684h

4

Message Signaled Interrupt Message Address (MSI_​MAD_​MMIO)

Package

00000000h

8688h

4

Message Signaled Interrupt Upper Address (MSI_​MUAD_​MMIO)

Package

00000000h

868ch

2

Message Signaled Interrupt Message Data (MSI_​MD_​MMIO)

Package

0000h

86a4h

4

High Speed Configuration 2 (HSCFG2_​MMIO)

Package

00000000h

8e10h

4

GLOBAL TIME SYNC CAP REG (GLOBAL_​TIME_​SYNC_​CAP_​REG)

Package

000012C9h

8e14h

4

GLOBAL TIME SYNC CTRL REG (GLOBAL_​TIME_​SYNC_​CTRL_​REG)

Package

00000000h

8e18h

4

MICROFRAME TIME REG (MICROFRAME_​TIME_​REG)

Package

00000000h

8e20h

4

Global Time Value (Low Register) (GLOBAL_​TIME_​LOW_​REG)

Package

00000000h

8e24h

4

GLOBAL TIME HI REG (GLOBAL_​TIME_​HI_​REG)

Package

00000000h

8e60h

4

Dublin HOST_​CTRL_​USB3_​LOCAL_​LPBK_​RPTR (HOST_​CTRL_​USB3_​LOCAL_​LPBK_​RPTR)

Package

00000000h

8ec8h

4

Host Ctrl Usb3 Master Loopback Register (HOST_​CTRL_​USB3_​MSTR_​LPBK)

Package

00000000h

8ecch

4

Host Ctrl Usb3 Blr Comp Register (HOST_​CTRL_​USB3_​BLR_​COMP)

Package

00000000h

8ed0h

4

Host Ctrl Ssp Dis Register (HOST_​CTRL_​SSP_​DIS)

Package

00000000h

90a4h

4

XHCI USB2 Overcurrent Pin Mapping (U2OCM1)

Package

00000000h

90a8h

4

XHCI USB2 Overcurrent Pin Mapping (U2OCM2)

Package

00000000h

90ach

4

XHCI USB2 Overcurrent Pin Mapping (U2OCM3)

Package

00000000h

90b0h

4

XHCI USB2 Overcurrent Pin Mapping (U2OCM4)

Package

00000000h

9124h

4

XHCI USB3 Overcurrent Pin Mapping (U3OCM1)

Package

00000000h

9128h

4

XHCI USB3 Overcurrent Pin Mapping (U3OCM2)

Package

00000000h

912ch

4

XHCI USB3 Overcurrent Pin Mapping (U3OCM3)

Package

00000000h

9130h

4

XHCI USB3 Overcurrent Pin Mapping (U3OCM4)

Package

00000000h
Capability Registers Length (CAPLENGTH)