Intel® Core™ Ultra Processors for H-series and U-series Platforms IOE-P I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795262 | 12/14/2023 | 001 | Public |
USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) – Offset 80f0
These set of registers is used to control jey USB set of timers. They are spread over 4 registers each 32 bits wide.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:11 | 0h | RO | Reserved |
| 10 | 0h | RW | Disable Port Error Detection (DIS_PERR_DET) 0: Enable Port Error Detection (default) |
| 9 | 1h | RW | Disable Peek Function for ISO-OUT (DIS_PF_IOUT) 0: Enable Peek function for ISO-OUT (default) |
| 8 | 1h | RW | Drive Resume-K FS/LS Serial Interface (DRV_RESK_FSLS_SER) 0: Drive Resume-K on parallel Interface |
| 7 | 1h | RW | Enable USB2 Drop-Ping (EN_U2_DROP_PING) 0: Disable Drop-Ping Function in USB2 Protocol (default) |
| 6 | 0h | RW | Enable USB2 Force-Ping (EN_U2_FORCE_PING) 0: Disable Force-Ping Function in USB2 Protocol (default) |
| 5 | 1h | RW | Enable USB2 Auto-Ping (EN_U2_AUTO_PING) 0: Disable Auto-Ping Function |
| 4 | 0h | RW | Disable PHY SuspendM (DIS_PHY_SUSM) 0: PHY is suspend=U3,U2,disconnect (default) |
| 3 | 0h | RW | UTMI Internal Clock Gate Disable (UTMI_INT_CG_DIS) 0: Normal operation (internal clock gated in U2,U3,disconnect) |
| 2 | 0h | RW | Disable PHY SuspendM in Disconnect State (DIS_PSUSM_DS) 0: PHY is suspendM=0 in Disconnect State (default) |
| 1:0 | 0h | RO | Reserved |