Pad Configuration Lock (PADCFGLOCK_GPP_E_0) – Offset 118 - 001 - ID:795260 | Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

ID	Date	Version	Classification
795260	12/14/2023	001	Public

Pad Configuration Lock (PADCFGLOCK_GPP_E_0) – Offset 118

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:25	0h	RO	Reserved (RSVD_0)
24	0h	RO	Reserved
23	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_23) PadCfgLock locks specific register fields in the pad specific registers (in Community or Pad) from being configured. The registers affected become Read-Only and software writes to these registers have no effect. This field is meaningful and takes effect only if the pad is owned by host (refer to PAD_OWN register). Pads under other ownership are not affected by the PadCfgLock. 0 = Unlock 1 = Lock the following register fields as read-only (RO): Pad Configuration registers (exclude GPIOTXState) GPI_NMI_EN Register (if implemented) HOSTSW_OWN Registers (if implemented) Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 \t\t\t
22	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_22) Same description as bit 0
21	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_21) Same description as bit 0
20	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_20) Same description as bit 0
19	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_19) Same description as bit 0
18	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_18) Same description as bit 0
17	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_17) Same description as bit 0
16	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_16) Same description as bit 0
15	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_15) Same description as bit 0
14	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_14) Same description as bit 0
13	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_13) Same description as bit 0
12	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_12) Same description as bit 0
11	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_11) Same description as bit 0
10	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_10) Same description as bit 0
9	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_9) Same description as bit 0
8	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_8) Same description as bit 0
7	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_7) Same description as bit 0
6	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_6) Same description as bit 0
5	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_5) Same description as bit 0
4	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_4) Same description as bit 0
3	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_3) Same description as bit 0
2	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_2) Same description as bit 0
1	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_1) Same description as bit 0
0	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_e_0) Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. This field takes effect only if the pad is owned by host (refer to PAD_OWN register). Pads under other ownership are not affected by the PadCfgLock. 0 = Unlock 1 = Lock the following register fields as read-only (RO): - Pad Configuration registers (exclude GPIOTXState) - GPI_NMI_EN Register (if implemented) - HOSTSW_OWN Registers (if implemented)