Status And Command (IDE_HOST_STS_CMD) – Offset 4 - 001 - ID:795260 | Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

ID	Date	Version	Classification
795260	12/14/2023	001	Public

Status And Command (IDE_HOST_STS_CMD) – Offset 4

This register contins the PCI status and command registers.

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Detected Parity Error (DPE) Not implemented. Hardwired to 0.
30	0h	RO	Signaled System Error (SSE) Not implemented. Hardwired to 0.
29	0h	RW/1C/V	Received Master Abort (RMA) This bit must be set by a master device whenever its transaction (except for Special Cycle) is completed with Unsupported Request Completion Status (a.k.a. Master-Abort).
28	0h	RW/1C/V	Received Target Abort (RTA) This bit must be set by a master device whenever its transaction is \t\tcompleted with Completer Abort Completion Status (a.k.a. Target-Abort). \t\tAll master devices must implement this bit.
27	0h	RW/1C/V	Signaled Target Abort (STA) This bit must be set by a target device whenever it completes a Posted or Non-Posted transaction with a Completer Abort (a.k.a. Target-Abort) error. Devices that will never signal Completer Abort (a.k.a. Target-Abort) do not need to implement this bit.
26:25	0h	RO	Devsel Timing (DEVT) These bits encode the timing of DEVSEL#. There are three allowable timings for assertion of DEVSEL# as described below: 00b: fast; 01b: medium; 10b: slow; 11b: reserved. Hardwired to 00b.
24	0h	RO	Master Data Parity Error (MDPE) Not implemented. Hardwired to 0.
23	1h	RO	Fast Back To Back Capable (FBTBC) This bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept these transactions and must be set to 0 otherwise. Hardwired to 1.
22	0h	RO	Reserved
21	1h	RO	66 Mhz Capable (MCAP) This bit indicates whether or not this device is capable of running at 66 MHz. A value of 0 indicates 33 MHz. A value of 1 indicates that the device is 66 MHz capable. Hardwired to 1.
20	1h	RO	Capabilities List (CAPL) This optional read-only bit indicates whether or not this device \t\timplements the pointer for a New Capabilities linked list at offset 34h. \t\tA value of zero indicates that no New Capabilities linked list is \t\tavailable. A value of one indicates that the value read at offset 34h is \t\ta pointer in Configuration Space to a linked list of new capabilities.
19	0h	RO	Interrupt Status (INTS) This read-only bit reflects the state of the interrupt in the device/function. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will the device's/function's INTx# signal be asserted. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Read-only and hardwired to 0 for a device that does NOT support pin-based interrupt.
18:11	0h	RO	Reserved
10	0h	RW	Interrupt Disable (INTD) This bit disables the device/function from asserting INTx#. 0: enables the assertion of its INTx# signal. 1: disables the assertion of its INTx# signal.
9	0h	RO	Fast Back To Back Enable (FBTBEN) Not implemented. Hardwired to 0.
8	0h	RO	System Error Enable (SERREN) Not implemented. Hardwired to 0.
7	0h	RO	Reserved
6	0h	RO	Parity Error Response (PERRR) Not implemented. Hardwired to 0.
5	0h	RO	VGA Palette Snoop (VGAPS) Not implemented. Hardwired to 0.
4	0h	RO	Memory Write And Invalidate Enable (MWRIEN) Not implemented. Hardwired to 0.
3	0h	RO	Special Cycles (SPCYC) Not implemented. Hardwired to 0.
2	0h	RW	Bus Master Enable (BME) Controls the ability of a PCI device to issue Memory and I/O Read/Write Requests, and the ability of a PCI bridge to forward Memory and I/O Read/Write Requests in the Upstream direction. Devices: When this bit is Set, the PCI device function is allowed to issue Memory or I/O Requests. When this bit is Clear, the PCI device function is not allowed to issue any Memory or I/O Requests. Note that as MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI-X interrupt Messages as well. Requests other than Memory or I/O Requests are not controlled by this bit. This bit is hardwired to 0b if a PCI device function does not generate Memory or I/O Requests. Bridges: This bit controls forwarding of Memory or I/O Requests by a bridge in the Upstream direction. When this bit is 0b, Memory and I/O Requests received at the Downstream side of a bridge must be handled as Unsupported Requests (UR), and for Non-Posted Requests . This bit does not affect forwarding of Completions in either the Upstream or Downstream direction. The forwarding of Requests other than Memory or I/O Requests is not controlled by this bit.
1	0h	RO	Memory Space Enable (MSE) Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to Memory Space accesses. Read-only and hardwired to 0 because IDE does NOT support Memory Space accesses.
0	0h	RW	IO Space Enable (IOSE) Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses.