Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 829568 | 05/27/2025 | 004 | Confidential |
Functional Description
The NPU IP comprises several individual components grouped into two major subsystems:
Details of these blocks are provided in the next sections.
Apart from the two major subsystems, the NPU has a Host interface for data exchange with the system memory.
Host Control
The functionality of the NPU is exposed to an processor via a base set of registers (enumerated as a PCIe device). These registers provide access to control and data path interfaces and reside in the Host Subsystem. All host communications are consumed by the NPU scheduler, a 64-bit RISC-V micro-controller. As well as responding to control messages it manages all the job submission/completion FIFOs that make up the data path of the NPU.
Deep Learning Accelerator
The NPU IP Deep Learning capability is provided by a configurable number of Neural Compute Engine (NCE) Tiles. The NCE Tiles are managed by the NPU Scheduler. Each Tile includes 1.5MB of near-compute SRAM, one Data Processing Unit (DPU) with 2048 INT8 Multiply Accumulators (MACs), and two DSPs for optimal processing of custom deep learning operations. The DSPs are the activation SHAVES (ACT-SHAVES). Global barriers and task FIFOs are also available for job synchronization and dispatch.
The NPU of Intel® Core™ Ultra 200V Series Processor comprises of 6 NCE Tiles, totaling 12k DPU INT8 MACs, 12 DSPs and 9 MB of associated near compute memory.
Below is the block diagram of NPU IP in Intel® Core™ Ultra 200V Series Processor