Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) – Offset c4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) – Offset c4

Bit Range	Default	Access	Field Name and Description
31	0b	RO/V	Component Property Parameter Table Valid (CPPTV) This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter Table in Component 0. Note: If this bit is set software must not overwrite bits that were initialized by hardware via SFDP discovery.
30	0b	RW/L	Vendor Component Lock (VCL) 0: The lock bit is not set 1: The Vendor Component Lock bit is set. This register locks itself when set.
29	0b	RW/V/L	64k Erase Valid (EO_64k_VALID) 0: The EO_64k opcode is not valid. 1: The EO_64k opcode is valid.
28	0b	RW/V/L	4k Erase Valid (EO_4k_VALID) 0: The EO_4k opcode is not valid. 1: The EO_4k opcode is valid.
27	0b	RW/L	RPMC Supported (RPMC_SUPPORTED) 0: The device does not support RPMC. 1: The device supports RPMC.
26	0b	RW/V/L	Deep Powerdown Supported (DEEP_PWRDN_SUPPORTED) 0: The device does not support Deep Powerdown. 1: The device supports Deep Powerdown.
25	0b	RW/V/L	Suspend/Resume Supported (SUSPEND_RESUME_SUPPORTED) 0: The device does not support Suspend/Resume. 1: The device supports Suspend/Resume.
24	0b	RW/V/L	Soft Reset Supported (SOFT_RST_SUPPORTED) 0: The device does not support Soft Reset. 1: The device supports Soft Reset.
23:16	00000000b	RW/V/L	64k Erase Opcode (EO_64k) This register is programmed with the Flash 64k sector erase instruction opcode for component 0. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit.
15:8	20h	RW/V/L	4k Erase Opcode (EO_4k) This register is programmed with the Flash 64k sector erase instruction opcode for component 0. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit.
7:5	000b	RW/V/L	Quad Enable Requirements (QER) 000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or because the manufacturer somehow permanently enables Quad capability. 001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status register clears all bits in register 2, therefore status register writes MUST be two bytes. 010 = Part requires bit 6 of status register 1 to be set to enable quad IO. 011 = Part requires bit 7 of the configuration register to be set to enable Quad. 100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the status register does not clear the second byte. This register is locked by the Vendor Component Lock (VCL) bit. If the SFDP table contains this information, the flash controller loads these bits from the table. The flash controller uses this information to prevent clearing the QE bit in the flash device's status register when WSR=1.
4	0b	RW/V/L	Write Enable on Write Status (WEWS) 0 = 50h is the opcode to enable a status register write 1 : 06h is the opcode to enable a status register write This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit. Note: Hardware ignores the state of this bit.
3	0b	RW/V/L	Write Status Required (WSR) 0 = No requirement to write to the Write Status Register prior to a write 1 = A write is required to the Write Status Register prior to write and erase to remove any protection. This is required for SST components. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit. Note: Hardware ignores the state of this bit.
2	0b	RW/V/L	Write Granularity (WG) 0 : Reserved 1 : 64 Byte This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit. Note: Hardware ignores the state of this bit.
1:0	-	-	Reserved

©Intel Corporation
Termos de uso
*Marcas comerciais
Privacidade
Cookies
Transparência da cadeira de fornecimento