12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2
Datasheet
ID
655258
Date
08/11/2021
Public Content
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Security Technologies
Intel® Trusted Execution Technology
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection
Intel® Supervisor Mode Access Protection
Intel® Secure Hash Algorithm Extensions
User Mode Instruction Prevention
Read Processor ID
Intel® Multi-Key Total Memory Encryption
Intel® Control-flow Enforcement Technology
KeyLocker Technology
Devil’s Gate Rock
Power and Performance Technologies
Intel® Smart Cache Technology
IA Cores Level 1 and Level 2 Caches
Ring Interconnect
Intel® Performance hybrid architecture
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology
Intel® Turbo Boost Technology 2.0
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology
Intel® GMM and Neural Network Accelerator
Cache Line Write Back
Remote Action Request
User Mode Wait Instructions
Power Management
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor AUX Power Management
Processor Graphics Power Management
System Agent Enhanced Intel SpeedStep® Technology
Rest Of Platform (ROP) PMIC
PCI Express* Power Management
TCSS Power State
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
Memory Controller Power Gate
System Memory Controller Organization Mode (DDR4/5 Only)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Signal Description
System Memory Interface
PCI Express* Graphics (PEG) Signals
Direct Media Interface (DMI) Signals
Reset and Miscellaneous Signals
Display Interfaces
Processor Clocking Signals
Testability Signals
Error and Thermal Protection Signals
Power Sequencing Signals
Processor Power Rails
Ground and Reserved Signals
Processor Internal Pull-Up / Pull-Down Terminations
Intel® APIC Virtualization Technology (Intel® APICv)
APIC virtualization is a collection of features that can be used to support the virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC).
When APIC virtualization is enabled, the processor emulates many accesses to the APIC, tracks the state of the virtual APIC, and delivers virtual interrupts — all in VMX non-root operation without a VM exit.
The following are the VM-execution controls relevant to APIC virtualization and virtual interrupts:
- Virtual-interrupt Delivery. This controls enables the evaluation and delivery of pending virtual interrupts. It also enables the emulation of writes (memory-mapped or MSR-based, as enabled) to the APIC registers that control interrupt prioritization.
- Use TPR Shadow. This control enables emulation of accesses to the APIC’s task-priority register (TPR) via CR8 and, if enabled, via the memory-mapped or MSR-based interfaces.
- Virtualize APIC Accesses. This control enables virtualization of memory-mapped accesses to the APIC by causing VM exits on accesses to a VMM-specified APIC-access page. Some of the other controls, if set, may cause some of these accesses to be emulated rather than causing VM exits.
- Virtualize x2APIC Mode. This control enables virtualization of MSR-based accesses to the APIC.
- APIC-register Virtualization. This control allows memory-mapped and MSR-based reads of most APIC registers (as enabled) by satisfying them from the virtual-APIC page. It directs memory-mapped writes to the APIC-access page to the virtual-APIC page, following them by VM exits for VMM emulation.
- Process Posted Interrupts. This control allows software to post virtual interrupts in a data structure and send a notification to another logical processor; upon receipt of the notification, the target processor will process the posted interrupts by copying them into the virtual-APIC page.
Intel® APIC Virtualization specifications and functional descriptions are included in the Intel® 64 Architectures Software Developer’s Manual, Volume 3. Available at: