0h

RO

0000000h

RW/P

ADDRESSLIMIT:

Limit address

Specifies the upper limit (inclusive) for address[51:26] (64MB aligned) to be part of this memory region.

An address hits a particular TAD entry if all of the following conditions are true (where number):

TadVld[N] == 1

address[51:26] <= AddressLimit[N]

address[51:26] > AddressLimit[N-1] (only for N>0)

System firmware must program the TAD AddressLimit fields such that AddressLimit[N] > AddressLimit[N-1] for all N>0 with TadVld[N]==1.

0h

RO

0h

RW/P

DEDUPVLD:

DedupRegion (DedupVld)

This TAD entry represents a region for which CHA uses Dedup IP to access memory

Setting this bit would mean m2mem would use a dedicated VC to issue transactions to the memory controller

which will be routed via the Dedup IP to MC

0h

RW/P

LOWBW:

Low Bandwidth Memory (LowBW):

This TAD entry represents a region for which CHA uses a low bandwidth credit.

Setting this bit causes m2mem to set the ddrt_​cdt bit on BL credit returns for writes

targeting this region.

0h

RW/P

FRCNPWR:

Force Non-Posted Writes (FrcNPWr):

This TAD entry represents region that requires NP write semantics on CMI.

Only applies to the far-memory region if this is a 2LM region.

0h

RW/P

SECONDARY1ST:

Read secondary mirror channel first (Secondary1st):

For this memory region, read secondary mirror channel first.

Used in mirroring to prevent (non error flow) accesses to a primary mirror

channel for a bad primary region/address. Note, if an error flow does get invoked

because of an error on secondary for an access to this region then the primary storage

will still be accessed (when channel not failed over).

0h

RW/P

MIRROR:

Mirror region:

This TAD entry represents a mirroring region.

0h

RW/P

NMCACHEABLEVLD:

Near-Memory Cacheable Valid (NmCacheableVld):

This TAD entry represents a near-memory cached region, that is, not a 1LM region.

0h

RW/P

DDR4:

DDR4:

This TAD entry represents near-memory at NMC or 1LM DDR4.

In non-Xtile config: this just represents the 1LM DDR4 region.

In Xtile config: this represents NM access at the near-memory controller (or DDR4 access at the FMC).

BIOS to calculate as follows:

0h

RW/P

BLKVLD:

Block Region Valid (BlkVld):

This TAD entry represents a block region.

0h

RW/P

PMEMVLD:

PMem Region Valid (PmemVld):

This TAD entry represents a persistent memory region.

0h

RW/P

NONPERSISTENTFM:

Non-Persistent Far Memory (NonPersistentFm):

This TAD entry represents a near-memory cached region in which the far-memory is non-persistent.

This bit only takes effect when NmCacheableVld for this TAD entry is set, and should only be set if

the far-memory being cached by near-memory is not persistent (that is, is not DDRT).

currently not supported where a single MC has both near-memory AND far-memory and the far-memory being

cached is not persistent/DDRT

0h

RO

0h

RW/P

DDRTADID:

DDR TAD entry (DDRtadId):

DDR TAD entry associated with this TAD table entry. M2mem puts no restrictions on the values here, but

this field should be programmed consistent with the channel

the channel, hence the current legal range is 0-11. DDR4 can only use the first 8 TAD entries, so the

legal range is 0-7 for regions with the DDR4 bit set.

HBM should only use TAD entry 0.

0h

RW/P

TADVLD:

TAD Table Entry Valid (TadVld):

Specifies whether this TAD entry in the TAD table is valid.

It is illegal to program TadVld[N]==1 if TadVld[N-1]==0 (for N>0).

0h

RW/V

TADWREN:

TAD Write (TadWrEn):

Write the TAD table entry with the information contained in this register.

Hardware will write the TAD table entry when seeing a zero-to-one transition on this bitfield.

Hardware will reset this bit to 0 the cycle after it is written to 1.

0h

RO

00h

RW/P

TADID:

TAD Table SAD Entry/Index (TadId):

Specifies what TAD entry in the TAD table to write indirectly through this register.

There are 20 TAD entries so the legal range is 0-19.