4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids
Data Sheet Vol. 2 Registers
Terminology
The following acronyms and terms are used in this document and related documentation.
| Term | Description |
|---|---|
| AC | Read and Write Access Control |
| ASPM | Active State Power Management |
| BL | Burst Length |
| BMC | Baseboard Management Controller |
| CA | Caching Agent |
| CHA | Caching and Home Agent |
| CP | Control Policy |
| CSR | Configuration Space Register |
| DDR5 | Fifth generation Double Data Rate SDRAM memory technology. |
| DMA | Direct Memory Access |
| DTLB | Data Translation Look-aside Buffer. Part of the processor core architecture. |
| DTS | Digital Thermal Sensor |
| ECC | Error Correction Code |
| EDAF | eSPI direct attached flash |
| EDP | Electrical Design Point |
| Enhanced Intel SpeedStep® Technology | Allows the operating system to reduce power consumption when performance is not needed. |
| Execute Disable Bit | The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual for detailed information. |
| FIVR | Fully Integrated Voltage Regulator |
| FLIT | Flow Control Unit. The Intel® UPI Link layer's unit of transfer. A FLIT is made of multiple PHITS. A Flit is always a fixed amount of information (192 bits). |
| Functional Operation | Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied. |
| GSSE | Extension of the SSE/SSE2 (Streaming SIMD Extensions) floating point instruction set to 256b operands. |
| HA | A Home Agent (HA) orders read and write requests to a piece of coherent memory. The HA is implemented in the CHA logic. |
| HDCC | High Density Core Count |
| ICU | Instruction Cache Unit. Part of the processor core architecture. |
| IFU | Instruction Fetch Unit. Part of the processor core. |
| IIO | Integrated I/O Controller. An I/O controller that is integrated in the processor die. |
| IMC | Integrated Memory Controller. A Memory Controller that is integrated in the processor die. |
| Intel® 64 Technology | 64-bit memory extensions to the IA-32 architecture. Further details on Intel® 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. |
| Intel® AVX | Intel® Advanced Vector Extensions promotes legacy 128-bit SIMD instruction sets that operate on XMM register set to use a "vector extension" (VEX) prefix and operates on 256-bit vector registers (YMM). |
| Intel® DLB | Intel® Dynamic Load Balancer (Intel® DLB) |
| Intel® DSA | Intel® Data Streaming Accelerator |
| Intel® IAA | Intel® In-Memory Analytics Accelerator |
| Intel Omni-Path | This is provided through a primary side connector on the package. |
| Intel® QAT | Intel® QuickAssist Technology is a platform solution designed to maximize the throughput of server data traffic across a broader range of configurations and server environments to achieve faster, scalable, and more reliable I/O. |
| Intel® TXT | Intel® Trusted Execution Technology |
| Intel® Turbo Boost Technology | A feature that opportunistically enables the processor to run a faster frequency. This results in increased performance of both single and multi-threaded applications. |
| Intel® UPI | Intel® Ultra Path Interconnect. A cache-coherent, link-based Interconnect specification for Intel® processors. |
| Intel® VT | Intel® Virtualization Technology. Processor Virtualization which, when used in conjunction with Virtual Machine Monitor software, enables multiple, robust independent software environments inside a single platform. |
| Intel® VT-d | Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel® VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O device Virtualization. Intel® VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel® VT-d. |
| Integrated Heat Spreader (IHS) | A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. |
| IOV | I/O Virtualization |
| IRP | I/O Request Packet (IRP) is the cache tracker for the IO M2 SSD |
| IVR | Integrated Voltage Regulation (IVR): The processor supports several integrated voltage regulators. |
| LLC | Last Level Cache |
| LRDIMM | Load Reduced Dual In-line Memory Module |
| LRU | Least Recently Used. A term used in conjunction with cache allocation policy. |
| M2M | Mesh to Memory. Logic in the IMC which interfaces the IMC to the mesh. |
| M2PCIe | The logic in the IIO modules which interface the modules to the mesh. |
| MCP | Multi-Chip Package |
| MESH | The on die interconnect that connects modules in the processor. |
| MESI | Modified/Exclusive/Shared/Invalid. States used in conjunction with cache coherency |
| MLC | Mid Level Cache |
| MSR | Model-Specific Register |
| NCTF | Non-Critical to Function: NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. |
| NID \ NodeID | Node ID (NID) or NodeID (NID). The processor implements up to 4- bits of NodeID (NID). |
| PBM | Power Budget Management |
| PCIe* | PCI Express* |
| Pcode | Pcode is microcode which is run on the dedicated microcontroller within the PCU. |
| PCU | Power Control Unit |
| PECI | Platform Environment Control Interface |
| Phit | The data transfer unit on Intel® UPI at the Physical layer is called a phit (physical unit). A Phit will be either 20 bits, or 8 bits depending on the number of active lanes. |
| Processor | Includes the 64-bit cores, uncore, I/Os and package |
| Processor Core | The term "processor core" refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache and data cache and Mid-Level Cache (MLC) cache. All execution cores share the L3 cache. |
| RAC | Read Access Control |
| Rank | A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DDR5 DIMM. |
| RAPL | Running Average Power Limit |
| RDIMM | Registered Dual In-line Memory Module |
| RTID | Request Transaction IDs are credits issued by the CHA to track outstanding transaction, and the RTIDs allocated to a CHA are topology dependent. |
| SCF | Scalable Coherent Fabric |
| SCI | System Control Interrupt. Used in ACPI protocol. |
| SKU | Stock Keeping Unit (SKU) is a subset of a processor type with specific features, electrical, power and thermal specifications. Not all features are supported on all SKUs. A SKU is based on specific use condition assumption. |
| RsvdP | Reserved and Preserved |
| RsvdZ | Reserved and Zero |
| SMBus | System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. |
| Storage Conditions | A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air"(that is,unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. |
| TAC | Thermal Averaging Constant |
| TDP | Thermal Design Power |
| TSOD | Temperature Sensor On DIMM |
| UDIMM | Unbuffered Dual In-line Memory Module |
| Unit Interval | Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t 1 , t 2 , t n ,...., t k then the UI at instance "n" is defined as: UI n = t n - t n-1 |
| VCCIN | Primary voltage input to the voltage regulators integrated into the processor. |
| VSS | Processor ground |
| VSSA | System agent supply for Intel® UPI and PCIe* |
| VCCIO | I/O voltage supply input |
| VCCD | DDR power rail |
| WAC | Write Access Control |
| x1, x4, x8, x16 | Refers to a link or port with one, four, eight, and sixteen physical lane(s). |