Eagle Stream Platform
Data Sheet
SMBus Memory Component Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the PIROM_ADDR[2:0] pins. These address pins are pulled down weakly (10k) on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus (or only support a partial implementation). The “Z” bit is the read/write bit for the serial bus transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be generated by an SMBus master.
Table: Memory Device SMBus Addressing describes the address pin connections and how they affect the addressing of the memory component.
| Address (Hex) | Upper Address1 | Device Select | R/W | ||
|---|---|---|---|---|---|
| Bits 7-4 | PIROM_ADDR[2] | PIROM_ADDR[1] | PIROM_ADDR[0] | Bit 0 | |
| A0h/A1h | 1010 | 0 | 0 | 0 | X |
| A2h/A3h | 1010 | 0 | 0 | 1 | X |
| A4h/A5h | 1010 | 0 | 1 | 0 | X |
| A6h/A7h | 1010 | 0 | 1 | 1 | X |
| A8h/A9h | 1010 | 1 | 0 | 0 | X |
| AAh/ABh | 1010 | 1 | 0 | 1 | X |
| ACh/ADh | 1010 | 1 | 1 | 0 | X |
| AEh/AFh | 1010 | 1 | 1 | 1 | X |