| Vcc1P8_PROC | Processor Power Rail voltage support PCIe (PHY) | S/S Refresh/P/PX/H/U Processor Lines | — | 1.8 | — | V | 3 |
| Vcc1P8_PROC | Processor Power Rail voltage support PCIe (PHY) | HX Processor Lines | — | 1.8 | — | V | 3 |
| TOB1P8_PROC | Vcc1P8_PROC Tolerance | All Processor Lines | ± 4 | % | 3,5 |
| AC Noise | AC Noise | All Processor Lines | — | — | +/-15 Frequency range from 1KHz Up to 10MHz +/-5 Frequency range Above 10MHz | mV | 6 |
| IccMAX_1P8_PROC | Maximum Current for Vcc1P8_PROC | P/H/PX/U-Processor Lines | — | — | 100 | mA | 4 |
| IccMAX_1P8_PROC | Maximum Current for Vcc1P8_PROC | S/S Refresh -Processor Line | — | — | 106 | mA | 4 |
| IccMAX_1P8_PROC | Maximum Current for Vcc1P8_PROC | HX-Processor Line | — | — | 140 | mA | 4 |
- All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
- Long term reliability cannot be assured in conditions above or below Maximum/Minimum functional limits.
- The voltage specification requirements are measured on capacitors pads near to the package, with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
- Vcc1P8_PROC power rail may be named in different document as Vcc1P8_CPU
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For S-process line, AC noise spec include VR self generated noise or input source AC noise that passes through to VR output and droop/overshoot due to transient load.
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